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Improving Output Voltage Swing in Cascode Current Mirrors

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Abstract

This work presents a technique to increase the output voltage swing of CMOS current mirrors which comprise stacked devices in their output branches, here generally referred as cascode current mirrors. The technique consists in replacing the primary output transistor by a network of four devices designed to anticipate the saturation onset. In such way, the cascode current mirror attains a reasonably higher-voltage compliance at its output, preserving other desirable features such as low output conductance and low mirroring error. The frequency bandwidth and power are not significantly affected. Simulation results on a 130-nm CMOS technology with 1.2-V supply voltage corroborate these observations: The increase in output voltage swing is within fifty to one hundred millivolts, while the increase in area is within 10–50% depending on circuit topology. This increase in area is much less than the resulting increase from re-dimensioning the circuit without the LSOT to achieve similar output voltage swing.

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Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

Code Availability

No code has been generated during the current study.

Notes

  1. In this context earlier means at lower VDS magnitude.

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Acknowledgements

Authors would like to acknowledge Conselho Nacional de Desenvolvimento Científico e Tecnológico—CNPq, Coordenação de Aperfeiçoamento de Pessoal de Nível Superior—CAPES, Fundação de Amparo à Pesquisa do Estado da Bahia—FAPESB and Sociedade Brasileira de Microeletrônica—SBMicro for the financial support.

Funding

This work received financial support from: Conselho Nacional de Desenvolvimento Científico e Tecnológico—CNPq, Coordenação de Aperfeiçoamento de Pessoal de Nível Superior—CAPES, Fundação de Amparo à Pesquisa do Estado da Bahia—FAPESB and Sociedade Brasileira de Microeletrônica—SBMicro.

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Authors and Affiliations

  1. Departamento de Engenharia Elétrica–Escola Politécnica, Universidade Federal da Bahia – UFBA, Rua Aristides Novis 2, Federação, Salvador, BA, 40210-630, Brazil

    Adson Alves Fernandes, Eliana Silva dos Santos, Mateus Moura Costa Simões, Lucas Costa D’Eça, Maicon Deivid Pereira & Ana Isabela Araújo Cunha

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  1. Adson Alves Fernandes
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Correspondence to Ana Isabela Araújo Cunha.

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Appendices

Appendix A

In CMOS technologies that use either LOCOS or STI as isolation techniques, charge sharing due to narrow widths affects the MOSFET threshold and saturation onset [26]. Therefore, the drain current variations with drain-to-source voltage are slightly different in MOS transistors with equal terminal voltages and equal lengths but with different widths. The ratio between their currents may even exhibit significant variation at low drain-to-source voltages. To illustrate this issue, we have simulated the DC output characteristics of several MOS transistors from a 130-nm CMOS technology, connected by the drain, source, gate and bulk terminals. The ratios between the drain currents of the pairs of transistors with equal channel lengths and different channel widths are depicted in Fig. 

Fig. 9
figure 9

Simulated normalized drain current ratios versus drain-to-source voltage VDS, for pairs of MOS transistors with: channel widths W1 = 2.00 µm and W2 = 20.00 µm (black lines); W1 = 2.00 µm and W2 = 0.20 µm (red lines); W1 = 0.20 µm and W2 = 20.00 µm (blue lines); channel length L = 0.12 µm (solid lines); channel length L = 2.00 µm (dashed lines). For all transistors: gate potential VG = 0.6 V, source and bulk potentials VS = VB = 0, drain terminals connected. Normalization constant: M = W2/W1 for each pair of transistors. Simulation software: SMASH; model: BSIM3v3; CMOS technology node: 130 nm

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9. These current ratios have been normalized by the ratio M between the MOSFET aspect ratios of each pair.

Appendix B

To verify whether the introduction of the LSOT network in the cascode mirror and in the RCCM contributes to improve output voltage compliance at lower supply voltages, DC output characteristics of the current mirrors with the sizes of Table 3 have been simulated for supply voltages between 1.2 and 0.8 V (reductions of up to 33%). In the cascode mirrors and LSOT-CM, it was not possible to properly dimension a simple current source able to provide the input current value of 10 µA at the mirror input for the constrained voltage room of 0.8 V. Hence the minimum supply voltage adopted in these cases was 0.9 V.

A similar verification has been accomplished for temperature deviations from the standard value of 27 °C. Thus, the DC output characteristics of the five configurations of cascode mirrors, LSOT-CM, RCCM and LSOT-RCCM have been simulated for temperatures of − 40 °C and 100 °C.

The results concerning the current mirrors with and without LSOT are compared through Fig. 

Fig. 10
figure 10

Comparison between cascode mirror and LSOT-CM (left) and between RCCM and LSOT-RCCM (right) for supply voltage variation: a difference between vOUTmin; b ratio between mean gOUT; c ratio between mean mirroring error ε

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10, for supply voltage variation, and through Fig. 

Fig. 11
figure 11

Comparison between cascode mirror and LSOT-CM (left) and between RCCM and LSOT-RCCM (right) for temperature variation: a difference between vOUTmin; b ratio between mean gOUT; c ratio between mean mirroring error ε

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11, for temperature variation, which present: (a) the differences between the values of vOUTmin without and with LSOT, (b) the ratios between the mean values of output conductance gOUT with and without LSOT and (c) the ratios between the mean values of mirroring error ε without and with LSOT. The mean values of gOUT and ε have been computed for the values of vOUT in the range between VDD/2 and VDD.

As can be seen in Fig. 10a, despite the reduction of the supply voltage, the differences between the values of vOUTmin without and with LSOT are positive, indicating that the substitution of the output primary transistor in the cascode mirror and in the RCCM promotes reduction of the minimum output voltage. Nevertheless, the lower the supply voltage smaller the voltage reduction. In Fig. 10b, the ratio between the mean values of output conductance gOUT with and without LSOT decreases, showing that the mean value of gOUT, in turn, becomes still smaller with LSOT application as supply voltage diminishes. In Fig. 10c, the comparison between RCCM and LSOT-RCCM shows a trend of error degradation with LSOT application as supply voltage is lowered, but no trend is observable in the comparison between cascode mirror and LSOT-CM.

In Fig. 11a, b, for both cascode mirror and RCCM, the LSOT application slightly improves vOUTmin and output conductance for all tested temperatures and more emphatically as temperature augments. The opposite behavior is verified for the mirroring error in Fig. 11c, except for the cascode mirror with 1-µA input current and mirror ratio M = 100.

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Fernandes, A.A., dos Santos, E.S., Simões, M.M.C. et al. Improving Output Voltage Swing in Cascode Current Mirrors. Circuits Syst Signal Process 42, 3268–3291 (2023). https://doi.org/10.1007/s00034-023-02293-7

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