Abstract
A high energy-efficient and reference voltage self-adaptive switching scheme for a triple-capacitive array successive approximation register analog-to-digital converters is proposed. The proposed switching time scheme includes Bi-level and Tri-level modes. The operating mode can be automatically switched by the reference voltage self-adaptive module according to the number of reference voltages of the peripheral circuits. The proposed timing scheme has the advantage of automatic compatibility with Bi/Tri-level reference voltage, which can be better adapted to the requirements of different hybrid ADC architectures. In Bi/Tri-level mode, two-step method, and monotonic switching scheme, floating capacitor technology is used to achieving 99.6% and 99.9% savings in average switching energy and a 73.4% reduction in total capacitance compared to the conventional scheme when applied to a 10-bit SAR ADC. The INL and DNL for both the Bi-level reference mode and the Tri-level reference mode are 0.350, 0.347 and 0.177, 0.172, respectively. In addition, the scheme eliminates to reset energy while regulating M to achieve a compromise between energy, area, and linearity. The post-simulation results show that the 10-bit SAR ADC with the proposed switching scheme can achieve a signal-to-noise distortion ratio (SNDR) of 60.53 dB and a spurious-free dynamic range (SFDR) of 68 dB at a sampling rate of 20 MS/s in a 65 nm CMOS process. The area of this ADC is only 0.2392 mm2.
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This work was supported by the National Natural Science Foundation of China (61804124), the Natural Science Basic Research Plan in Shaanxi Province of China (2021JQ-718).
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Appendix: Without Reset Energy Consumption of Eqs. (16)–(33)
Appendix: Without Reset Energy Consumption of Eqs. (16)–(33)
The reset energy consumption of the proposed Bi-level reference voltage capacitor switching structure is shown in the following mathematical derivation.
The value of the VFP2 voltage changed and the energy consumed by the voltage flip for this process is zero, as evidenced by the following equation:
The value of the voltage changes of VCP2 and the energy consumed by the voltage flip as shown in (19):
The value of the voltage changes of VFN2 and the energy consumed is:
The value of the voltage changes of VCN2 and the energy consumed by the voltage flip is proved and is calculated below:
Thus, the total energy consumption of the Bi-level reference voltage scheme is:
The reset energy consumption of the proposed Tri-level reference voltage capacitor switching structure is calculated by the following equation.
The value of the VFP2 voltage changed and the energy consumed by the voltage flip for this process is zero, as evidenced by the following mathematical derivation:
The value of the voltage changes of VCP2 and the energy consumed by the voltage flip is proved by the following equation:
The value of the voltage changes of VFN2 and the energy consumed by the voltage flipped is proved and calculated below:
The value of the voltage changes of VCN2 and the energy consumed by the voltage flipped is proved by the following expression:
The total energy consumption of the Tri-level-based voltage scheme is:
Conclusion: The proposed Bi-level reference voltages and Tri-level reference voltages have no reset energy consumption. The analysis shows that there is no switch to the ports of the capacitor array and the comparator and that the voltage of each capacitor on the bottom plate of the capacitor array is not consistent. This will exist to reset the energy consumption.
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Dong, S., Liu, C., Bu, S. et al. A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs. Circuits Syst Signal Process 42, 4470–4505 (2023). https://doi.org/10.1007/s00034-023-02352-z
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DOI: https://doi.org/10.1007/s00034-023-02352-z