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Design of a Power-Performance-Area (PPA) Optimized MOS Current Mode Logic Pre-scaler

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Abstract

This work presents a design of a power-performance-area optimized MOS current mode logic pre-scaler. The divide-by-3 pre-scaler is realized in TSMC 180 nm technology node. The post-layout simulation results show that the proposed pre-scaler can operate faithfully up to 10.58 GHz operating frequency in the worst speed corner with a maximum power dissipation of 2.86 mW at the worst power corner. The divider occupies 0.115 × 0.128 mm2 area. The overall performance trade-off presents the figure of merit: FoM of 24 dB, which shows a better trade-off when compared with the state of the art. The impact of PVT variations is also analyzed.

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Acknowledgements

The authors would like to thank the Ministry of Electronics and Information Technology (MeitY), Govt. of India, for extending technical and financial support through Visvesvaraya Ph.D. Scheme (Unique Awardee Number: VISPHD-MEITY-1543).

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Sikkim, Ravangla, 737139, Sikkim, India

    Subhanil Maity & Sanjay Kumar Jana

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  1. Subhanil Maity
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  2. Sanjay Kumar Jana
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Correspondence to Subhanil Maity.

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Maity, S., Jana, S.K. Design of a Power-Performance-Area (PPA) Optimized MOS Current Mode Logic Pre-scaler. Circuits Syst Signal Process 42, 5783–5798 (2023). https://doi.org/10.1007/s00034-023-02394-3

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