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Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance

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Abstract

A decoupled inverter pair sense amplifier (DIPSA) is proposed for improved sensing in differential SRAM. The DIPSA is designed at 45-nm technology node with a decreased sensing delay of 31.44% and 28.44% over the conventional latch-type sense amplifier (CLSA) and current-latched SA with an NMOS footswitch (CSANF) at 1.1 V, respectively. The performance of DIPSA is validated using delay and power consumption comparison with prior SA designs across a set of supply voltages. Monte Carlo simulation for 3\(\sigma \) deviation yields a reliable design with no read failures and mean delay of 488.81 ps across the 1k data points with a deviation of 54.87 ps. The threshold voltage variation contribution to process variation is considered for these calculations. The sizing of the decoupling transistors is discussed and its impact on the delay and power of DIPSA shown. The performance of existing voltage and current sense amplifiers is compared to DIPSA.

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  1. Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, 110042, India

    Ayush Dahiya, Poornima Mittal & Rajesh Rohilla

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  1. Ayush Dahiya
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  2. Poornima Mittal
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  3. Rajesh Rohilla
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Correspondence to Poornima Mittal.

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Dahiya, A., Mittal, P. & Rohilla, R. Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance. Circuits Syst Signal Process 42, 5799–5810 (2023). https://doi.org/10.1007/s00034-023-02397-0

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