Abstract
This article presents a reconfigurable rotation mode coordinate rotation digital computer (CORDIC) algorithm that can be configured in hyperbolic or circular trajectories. The proposed CORDIC algorithm employs the new angle set to acquire the absolute scaling-free rotation in circular or hyperbolic trajectories. The proposed new angle set is represented using only power of two terms, which helps to compute the rotation using only shift and add architecture. The effective word length is taken as a measure to check the accuracy of the proposed angle set. The original scaling-free CORDIC algorithm has a limited range of convergence from \(-\dfrac{\pi }{4}\) to \(\dfrac{\pi }{4}\). The proposed algorithm achieves the convergence range from \(-\dfrac{\pi }{2}\) to \(\dfrac{\pi }{2}\) through a new proposed angle set. In the proposed angle set, the power of the two terms used to represent the hyperbolic and circular rotations are similar, resulting in an architecture with a minimum reconfiguration resource. The first four stages rotate the rotating vector through the proposed angle set to bring down the rotation angle to a minimum value, which enables the use of the Taylor approximation for successive stages without any error. The last two stages use the first-order Taylor series approximation to realize the scaling-free rotation. The fully pipelined architecture is described using Verilog HDL and synthesized to map on Virtex-5 field-programmable gate arrays using the Xilinx Vivado design suite. The synthesis results suggest that the proposed CORDIC architecture uses 23.03% and 19.36% fewer resources as compared to architectures (Aggarwal and Meher, in: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014) and (Aggarwal et al. in IEEE Trans Very Large Scale Integr. (VLSI) Syst 24(4):1588–1592, 2016), respectively.
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References
S. Aggarwal, P.K. Meher, Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations, in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (2014), pp. 2490–2494. https://doi.org/10.1109/ISCAS.2014.6865678
S. Aggarwal, P.K. Meher, K. Khare, Area-time efficient scaling-free CORDIC using generalized micro-rotation selection. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(8), 1542–1546 (2012). https://doi.org/10.1109/TVLSI.2011.2158459
S. Aggarwal, P.K. Meher, K. Khare, Scale-free hyperbolic CORDIC processor and its application to waveform generation. IEEE Trans. Circuits Syst. I Regul. Pap. 60(2), 314–326 (2013). https://doi.org/10.1109/TCSI.2012.2215778
S. Aggarwal, P.K. Meher, K. Khare, Concept, design, and implementation of reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(4), 1588–1592 (2016). https://doi.org/10.1109/TVLSI.2015.2445855
E. Antelo, J. Villalba, J.D. Bruguera, E.L. Zapata, High performance rotation architectures based on the radix-4 CORDIC algorithm. IEEE Trans. Comput. 46(8), 855–870 (1997). https://doi.org/10.1109/12.609275
E. Antelo, J. Villalba, E.L. Zapata, A low-latency pipelined 2D and 3D CORDIC processors. IEEE Trans. Comput. 57(3), 404–417 (2008). https://doi.org/10.1109/TC.2007.70796
D.D. Caro, N. Petra, A.G.M. Strollo, A 380 MHz direct digital synthesizer/mixer with hybrid CORDIC architecture in 0.25 \(\mu \)m CMOS. IEEE J. Solid-State Circuits 42(1), 151–160 (2007). https://doi.org/10.1109/jssc.2006.886527
D.D. Caro, N. Petra, A.G.M. Strollo, Digital synthesizer/mixer with hybrid CORDIC-multiplier architecture: error analysis and optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 56, 364–373 (2009). https://doi.org/10.1109/TCSI.2008.2001370
A. Changela, M. Zaveri, D. Verma, FPGA implementation of high-performance, resource-efficient radix-16 CORDIC rotator based FFT algorithm. Integration 73, 89–100 (2020). https://doi.org/10.1016/j.vlsi.2020.03.008
A. Changela, M. Zaveri, D. Verma, Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications. Integration 78, 70–83 (2021). https://doi.org/10.1016/j.vlsi.2021.01.005
A. Changela, M. Zaveri, D. Verma. A comparative study on CORDIC algorithms and applications. J. Circuits Syst. Comput. 32(05) (2022). https://doi.org/10.1142/s0218126623300027
H. Chen, K. Cheng, Z. Lu, Y. Fu, L. Li, Hyperbolic CORDIC-based architecture for computing logarithm and its implementation. IEEE Trans. Circuits Syst. II Express Briefs 67(11), 2652–2656 (2020). https://doi.org/10.1109/TCSII.2020.2971974
L. Fang, B. Li, Y. Xie, H. Chen, L. Pang, A unified reconfigurable CORDIC processor for floating-point arithmetic. Int. J. Electron. 107(9), 1436–1450 (2020). https://doi.org/10.1080/00207217.2020.1726497
M. Garrido, O. Gustafsson, J. Grajal, Accurate rotations based on coefficient scaling. IEEE Trans. Circuits Syst. II Express Briefs 58(10), 662–666 (2011). https://doi.org/10.1109/tcsii.2011.2164144
M. Garrido, P. Källström, M. Kumm, O. Gustafsson, CORDIC II: a new improved CORDIC algorithm. IEEE Trans. Circuits Syst. II Express Briefs 63(2), 186–190 (2016). https://doi.org/10.1109/TCSII.2015.2483422
M. Garrido, F. Qureshi, O. Gustafsson, Low-complexity multiplierless constant rotators based on combined coefficient selection and shift-and-add implementation (CCSSI). IEEE Trans. Circuits Syst. I Regul. Pap. 61(7), 2002–2012 (2014). https://doi.org/10.1109/tcsi.2014.2304664
H. Huang, L. Xiao, J. Liu, CORDIC-based unified architectures for computation of DCT/IDCT/DST/IDST. Circuits Systems Signal Process. 33, 799–814 (2014). https://doi.org/10.1007/s00034-013-9661-9
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata, Enhanced scaling-free CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. 57(7), 1654–1662 (2010). https://doi.org/10.1109/TCSI.2009.2037391
T. Kulshreshtha, A. Dhar, Cordic-based high throughput sliding dft architecture with reduced error-accumulation. Circuits Syst. Signal Process. 37, 5101–5126 (2018). https://doi.org/10.1007/s00034-018-0810-z
B. Lakshmi, A. Dhar, VLSI architecture for low latency radix-4 CORDIC. Comput. Electr. Eng. 37(6), 1032–1042 (2011). https://doi.org/10.1016/j.compeleceng.2011.07.011
C.-H. Lin, A.-Y. Wu, Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications. IEEE Trans. Circuits Syst. I Regul. Pap. 52(11), 2385–2396 (2005). https://doi.org/10.1109/tcsi.2005.853908
Y. Liu, L. Fan, T. Ma, A modified CORDIC FPGA implementation for wave generation. Circuits Syst. Signal Process. 33, 321–329 (2014). https://doi.org/10.1007/s00034-013-9638-8
Y. Luo, Y. Wang, Y. Ha, Z. Wang, S. Chen, H. Pan, Generalized hyperbolic CORDIC and its logarithmic and exponential computation with arbitrary fixed base. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(9), 2156–2169 (2019). https://doi.org/10.1109/TVLSI.2019.2919557
F. Lyu, X. Xu, Y. Wang, Y. Luo, Y. Wang, H. Pan, Ultralow-latency VLSI architecture based on a linear approximation method for computing \(n^{th}\) roots of floating-point numbers. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2), 715–727 (2021). https://doi.org/10.1109/TCSI.2020.3038417
K. Maharatna, S. Banerjee, E. Grass, M. Krstic, A. Troya, Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture. IEEE Trans. Circuits Syst. Video Technol. 15(11), 1463–1474 (2005). https://doi.org/10.1109/TCSVT.2005.856908
K. Maharatna, A. Troya, S. Banerjee, E. Grass, Virtually scaling-free adaptive CORDIC rotator. IEE Proc. Comput. Digit. Tech. 151, 448–456 (2004). https://doi.org/10.1049/ip-cdt:20041107
H. Mahdavi, S. Timarchi, Area-time-power efficient FFT architectures based on binary-signed-digit CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. 66(10), 3874–3881 (2019). https://doi.org/10.1109/TCSI.2019.2922988
P.K. Meher, J. Valls, T. Juang, K. Sridharan, K. Maharatna, 50 years of CORDIC: algorithms, architectures, and applications. IEEE Trans. Circuits Syst. I Regul. Pap. 56(9), 1893–1907 (2009). https://doi.org/10.1109/TCSI.2009.2025803
S. Mopuri, A. Acharyya, Configurable rotation matrix of hyperbolic CORDIC for any logarithm and its inverse computation. Circuits Syst. Signal Process. 39 (2020). https://doi.org/10.1007/s00034-019-01277-w
Y. Parmar, K. Sridharan, Precomputation-based radix-4 CORDIC for approximate rotations and hough transform. IET Circuits Devices Syst. 12(4), 413–423 (2018). https://doi.org/10.1049/iet-cds.2017.0492
R. Shukla, K.C. Ray, Low latency hybrid CORDIC algorithm. IEEE Trans. Comput. 63(12), 3066–3078 (2014). https://doi.org/10.1109/TC.2013.173
T. Sung, Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations. IEE Proc. - Vis. Image Signal Process. 153(4), 405–410 (2006). https://doi.org/10.1049/ip-vis:20045148
J. E. Volder, The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput. EC-8(3), 330–334 (1959). https://doi.org/10.1109/TEC.1959.5222693
J.E. Volder, The birth of CORDIC. J. VLSI Signal Process. Syst. Signal Image Video Technol. 25, 101–105 (2000). https://doi.org/10.1023/A:1008110704586
P. Vyas, L. Vachhani, K. Sridharan, V. Pudi, CORDIC-based azimuth calculation and obstacle tracing via optimal sensor placement on a mobile robot. IEEE/ASME Trans. Mechatron. 21(5), 2317–2329 (2016). https://doi.org/10.1109/TMECH.2015.2502622
J. S. Walther, A unified algorithm for elementary functions, in Proceedings of the May 18-20, 1971, Spring Joint Computer Conference, AFIPS’71 (Spring) (Association for Computing Machinery, New York, NY, USA, 1971), pp. 379–385. https://doi.org/10.1145/1478786.1478840
J.S. Walther, The story of unified CORDIC. J. VLSI Signal Process. Syst. Signal Image Video Technol. 25(2), 107–112 (2000). https://doi.org/10.1023/A:1008162721424
Y. Wang, Y. Luo, Z. Wang, Q. Shen, H. Pan. GH CORDIC-based architecture for computing \(n^{th}\) root of single-precision floating-point number. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(4), 864–875 (2020). https://doi.org/10.1109/TVLSI.2019.2959847
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Changela, A., Zaveri, M. & Kumar, Y. A New Angle Set-Based Absolute Scaling-free Reconfigurable Cordic Algorithm. Circuits Syst Signal Process 42, 7404–7432 (2023). https://doi.org/10.1007/s00034-023-02452-w
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DOI: https://doi.org/10.1007/s00034-023-02452-w