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A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

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Abstract

This paper presents a low-power multi-rate clock and data recovery (CDR) for receivers of serial links. Its basic structure includes a current-mode logic bang–bang phase detector sampled by low-mismatch half-rate quadrature clocks, which are generated by voltage-controlled delay line (VCDL) and two-stage time-average circuits. The total delay of VCDL can be adjusted to accommodate a wide frequency range by its bias voltage, which is generated by a delay-locked-loop-based bias generator. The quadrature clocks are 64-phase adjustable with high linearity, which is realized by phase interpolator with a compensating structure. The parameters of phase detection loop are well designed to satisfy both high jitter tolerance and low clock jitter. Fabricated in a 40 nm CMOS technology, the CDR occupies an active area of 0.036 mm\(^2\) only. With a wide operating range of 2–20 Gb/s, the chip consumes 62.5 mW, corresponding to an energy efficiency of 3.1 pJ/bit. The measured root-mean-square jitter and peak-to-peak jitter for the recovered clock at 9 GHz are 1.9 and 10.8 ps, respectively.

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Acknowledgements

This work was supported by the National Major Research and Development Program (Grant No. 2022YFB2803100) and National Natural Science Foundation of China (Grant No. 61974022).

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Author notes

  1. Yingmei Chen, Wentian Fan, Qingyi Zhao, En Zhu and Zhengfei Hu have contributed equally to this work.

Authors and Affiliations

  1. Institute of RF and OE-ICs, Southeast University, Nanjing, 210096, Jiangsu, China

    Yinghao Chen, Yingmei Chen, Wentian Fan, Qingyi Zhao & En Zhu

  2. Pervasive Communication Research Department, Purple Mountain Laboratories, Nanjing, 211111, Jiangsu, China

    Yingmei Chen

  3. College of Science, Nanjing University of Posts and Telecommunications, Nanjing, 210023, Jiangsu, China

    Zhengfei Hu

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  1. Yinghao Chen
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  2. Yingmei Chen
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Correspondence to Yingmei Chen.

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Chen, Y., Chen, Y., Fan, W. et al. A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop. Circuits Syst Signal Process 43, 318–330 (2024). https://doi.org/10.1007/s00034-023-02473-5

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