Abstract
Today, the main concern of digital circuit designers is reducing the power of portable equipment due to the limitation of charging their batteries. One of the ways to reduce power consumption is to use approximate units in systems that have the ability to tolerate faults. Another solution to consider is designing circuits with Multi-Valued Logic (MVL), which can also reduce power consumption. The use of CNTFET transistors in MVL circuit designs can lead to higher efficiency in integrated circuits, particularly in terms of power, speed and area. Full adders are essential arithmetic modules in processors and serve as the cornerstone of digital systems. In this research study, we aimed to design an Approximate Ternary Full Adder (ATFA) with the minimum number of transistors and power consumption. Based on simulations conducted using Synopsys HSPICE in Stanford's 32 nm CNTFET technology, the proposed ATFA design demonstrated superior performance compared to previous similar designs, particularly in terms of average power consumption, delay, and energy consumption. In addition, according to the examination of noise immunity curves, the proposed circuit has higher pulse noise amplitude in all pulse widths than other circuits. Meanwhile, at the program level, image composition has been considered to study accuracy criteria such as peak Signal-to-Noise Ratio (PSNR), Structural Similarity (SSIM), and Figures Of Merit (FOM) in image synthesis, supported the superior performance of our proposed circuit compared to other similar circuits.
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References
G. Anusha, P. Deepa, Design of approximate adders and multipliers for error-tolerant image processing. Microprocess. Microsyst. 72, 102940 (2020). https://doi.org/10.1016/j.micpro.2019.102940
P.C. Balla, A. Antoniou, Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits 19, 739 (1984). https://doi.org/10.1109/JSSC.1984.1052216
Y. Bok Kim, Y. B. Kim F. Lombardi, novel design methodology to optimize the speed and power of the CNTFET circuits. In Proc. 2009 IEEE Internationl. Midwest Symposium on Circuits and Systems, 1130 (2009). https://doi.org/10.1109/MWSCAS.2009.5235967
G. Cho, F. Lombardi, Design and process variation analysis of CNTFET-based ternary memory cells. Integr. VLSI J. 54(c), 97 (2016). https://doi.org/10.1016/j.vlsi.2016.02.003
J. Deng, Ph.D. thesis, Stanford University, device modeling and circuit performance evaluation for nanoscale device: silicon technology beyond 45 nm node ancarbon nanotube field effect transistors, (2007).
J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube fieldeffect transistors including nonidealities and its application–part I: model of the intrinsic channel region. IEEE Trans. Electron. Devi. 54(12), 3186 (2007). https://doi.org/10.1109/TED.2007.909030
J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube fieldeffect transistors including nonidealities and its application–part II: full device model and circuit performance benchmarking. IEEE Trans. Electron. Dev. 54(12), 3195 (2007). https://doi.org/10.1109/TED.2007.909043
E. Dubrova, Multiple-valued logic in VLSI: challenges and opportunities. Proc. NORCHIP 99, 340–350 (1999)
T. Erik, Z. Renb, T. Chou, Advances in the science and technology of carbon nanotubes and their composites: a review. Compos. Sci. Technol. 61(13), 1899 (2001). https://doi.org/10.1016/S0266-3538(01)00094-X
N. Hajizadeh Bastani, M.H. Moaiyeri, K. Navi, An Energy- and area-efficient approximate ternary adder based on CNTFET switching logic. Circuits Syst. Signal Process. 37, 1863 (2018). https://doi.org/10.1007/s00034-017-0627-1
J. Huang, T. Nandha Kumar and H. Abbas, Simulation-based evaluation of approximate adders for image processing using voltage overscaling method, IEEE 5th International Conference on Signal and Image Processing (ICSIP), 499 (2020). https://doi.org/10.1088/1742-6596/1962/1/012050
J. Huang, M. Zhu, P. Gupta, S. Yang, S. M. Rubin, G. Garret, and J. He, “A CAD tool for design and analysis of CNFET circuits. IEEE Int. Conf. Electron Devices and Solid-State Circuits, Hong Kong, p. 1 (2010) https://doi.org/10.1109/EDSSC.2010.5713735
M. Huang, S. Zhu, P. Yang, W. Gupta, S.M. Zhang, G. Rubin, J.H. Garreton, A physical design tool for carbon nanotube field-effect transistor circuits. ACM J. Emerg. Technol. Comput. Syst. 8, 1 (2012). https://doi.org/10.1145/2287696.2287708
Home of the electric VLSI design system website, available at http://www.staticfreesoft.com/index.html
S.L. Hurst, Multiple-valued logic- its status and its future. IEEE Trans. Comput. C–33(12), 1160 (1984). https://doi.org/10.1109/TC.1984.1676392
N.V. Karimi, Y. Pourasad, Investigating the effect of some parameters of the channel on the characteristics of tunneling carbon nanotube field-effect transistor. Int. Nano Lett. 6, 215–221 (2016). https://doi.org/10.1007/s40089-016-0182-y
J. Liang, J. Han, F. Lombardi, New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Comput. 62(9), 1760 (2013). https://doi.org/10.1109/TC.2012.146
S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Transact. Nanotechnol. 10, 217 (2011). https://doi.org/10.1109/TNANO.2009.2036845
S. Ijiima, Helical microtubules of graphitic carbon. Nature 354, 56 (1991). https://doi.org/10.1038/354056a0
M. Mahjoubi, M. Dadashi, K. Manochehri, S. Pourmozafari, Two Efficient ternary adder designs based on CNFET technology. Comput. Knowl. Eng. 4(1), 25–34 (2021). https://doi.org/10.22067/cke.2021.70110.1009
M. Malik, S. Hussain and M. Hasan, An approximate ternary full adder using Carbon nanotube field effect transistors, 2022 5th International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT), Aligarh, India, 1–6, (2022) https://doi.org/10.1109/IMPACT55510.2022.1002915
M. Maleknejad, R. Faghih Mirzaee, K. Navi Keivan, O. Hashemipour, Multi-Vt ternary circuits by carbon nanotube filed effect transistor technology for low-voltage and low-power applications. J. Comput. Theor. Nanosci. 11(1), 110 (2014). https://doi.org/10.1166/jctn.2014.3324
A. Mohammadi, M. Mohammadi Ghanatghestani, A. Sabbagh Molahosseini, Y. Safaei Mehrabani, High-performance and energy-area efficient approximate full adder for error tolerant applications. ECS J. Solid State Sci. Technol. (2022). https://doi.org/10.1149/2162-8777/ac861c
A. Mohammadi, M. Mohammadi Ghanatghestani, A. Sabbagh Molahosseini, Y. Safaei Mehrabani, Image processing with high-speed and low-energy approximate arithmetic circuit. Sustain. Comput. Inform. Syst. 36, 100781 (2022). https://doi.org/10.1016/j.suscom.2022.100781
K. Navi, R. Sharifi Rad, M.H. Moaiyeri, A. Momeni, A low-voltage and energy-efficient full adder cell based on carbon nanotube technology. Nano-Micro Lett. 2, 114 (2010). https://doi.org/10.1007/BF03353628
A. Neelam, P. Manisha, G.K. Sharma, Energy-efficient logarithmic square rooter for error-resilient applications. IEEE Transact. Very Large Scale Integ. (VLSI) Syst. 29(11), 1994–1997 (2021)
A. Niedzicka, Computation-intensive image processing algorithm parallelization on multiple hardware architectures, Proceedings. International Conference on Parallel Computing in Electrical Engineering, Warsaw, Poland. 25 (2002) https://doi.org/10.1109/PCEE.2002.1115341
A. Panahi, F. Sharifi, M.H. Moaiyeri, K. Navi, CNFET-based approximate ternary adders for energyefficient image processing applications. Microprocessors 47(Part B), 454 (2016). https://doi.org/10.1016/j.micpro.2016.07.015
M.C. Parameshwara, Approximate full adders for energy efficient image processing applications. J. Circuits, Syst. Comput. 30(13), 2150235 (2021). https://doi.org/10.1142/S0218126621502352
A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. 54(11), 2391 (2007). https://doi.org/10.1109/TCSI.2007.907799
A. Raychowdhury, Student Member, IEEE, Ali Keshavarzi, Member, IEEE, Juanita Kurtin, Vivek De, and Kaushik Roy, Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure, Fellow, IEEE Transactions on Electron Devices, 53(11), (2006) https://ieeexplore.ieee.org/document/1715613
A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Transact. Nanotechnol. 4(2), 168 (2005). https://doi.org/10.1109/TNANO.2004.842068
K. Roy, S. Mukhopadhyay, H. Meirmandi, Leakage current mechanisms and leakage reduction technologies in deep-submicron CMOS circuits. Proc. IEEE 91(2), 305 (2003)
J.N. Roy, T. Chattopadhyay, All-optical quaternary logic based information processing: challenges and opportunities, in Design and Architectures for Digital Signal Processing (InTech, Croatia, pp. 81 (2013) https://doi.org/10.5772/51559
Y. Safaei Mehrabani and M. Eshghi, Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology. IEEE Transact. Very Large Scale Integr. VLSI Syst., 24(11), 3268 (2016) https://doi.org/10.1109/TVLSI.2016.2540071
Y. Safaei Mehrabani, M. Mohammadi Ghanatghestani, R. Sharifirad, A.M. Hassanzadeh, Power-efficient and high-speed design of approximate full adders using CNFET technology. Int. J. Nano Dimens. 13(2), 179 (2022). https://doi.org/10.22034/ijnd.2022.686218
Y. Safaei Mehrabani, M.H. Shafiabadi, A novel high-performance and reliable multi-threshold CNFET full adder cell design. Int. J. High Perform. Systems Archit. 7, 15 (2017). https://doi.org/10.1504/IJHPSA.2017.083644
K. El-Shabrawy, K. Maharatna, D. Bagnall, B.M. Al-Hashimi, Modeling SWCNT bandgap and effective mass variation using a monte carlo approach. IEEE Trans. Nanotechnol. 9, 184 (2010). https://doi.org/10.1149/2162-8777/ac861c
M. Shafique, L. Bauer and J. Henkel, enBudget: a Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder, Design, Automation & Test in Europe Conference & Exhibition .Dresden, Germany, 08–12 March (2010) https://doi.org/10.1109/DATE.2010.5457093
S.K. Sinha, and S. Chaudhury, Simulation and Analysis Of Quantum Capacitance In Single-Gate MOSFET, Double-Gate MOSFET and CNTFET Devices For Nanometre Regime, 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS) https://doi.org/10.1109/CODIS.2012.6422160
K. Tanaka, T. Yamabe, K. Fukui, The science and technology of carbon nanotubes. 639 (1997). https://doi.org/10.1080/10641220009351440
X. Wu, F. Prosser, CMOS ternary logic circuits. IEE Proc. G Circuits Dev. Syst 137, 21 (1990). https://doi.org/10.1049/IP-G-2.1990.0005
Q. Xu, T. Mytkowicz, N.S. Kim, Approximate computing: a survey. IEEE Design Test. 33(1), 8 (2016). https://doi.org/10.1109/MDAT.2015.2505723
Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices. IEEE J. Solid-State Circuits 21, 162 (1986)
A.J. Yang, J. Liang, J. An, F. Lombardi, Approximate XOR/XNOR-based adders for inexact computing. In Nanotechnology (IEEE-NANO), 2013 13th IEEE Conference, 690 (2013). https://doi.org/10.1109/NANO.2013.6720793
M. Yousefi, Z. Moradi, K. Monfaredi, CNTFET based pseudo ternary adder design and simulation. AUT J. Elec. Eng. 54(2), 361–376 (2022). https://doi.org/10.22060/eej.2022.20853.5443
X. Zhao, M. Ohkohchi, M. Wang, S. Lijima, T. Ichihashi, Y. Ando, Carbon 35(6), 775 (1997). https://doi.org/10.1016/S0008-6223(97)00033-X
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Sharifi Rad, R., Mohammadi Ghanatghestani, M. & Hashemipour, M. Efficient ATFA design based on CNTFET technology for error–tolerant applications. Circuits Syst Signal Process 43, 1119–1143 (2024). https://doi.org/10.1007/s00034-023-02506-z
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DOI: https://doi.org/10.1007/s00034-023-02506-z