Abstract
An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2.
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Acknowledgements
This work is supported in part by the National Natural Science Foundation of China (Nos. 62104193 and 62271389), the Key Scientific Research Program of Shaanxi Provincial Department of Education (No. 22JY058).
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Xin, X., Zhang, C. & Tong, X. An 11-bit Nyquist SAR-VCO Hybrid ADC with a Reused Ring-VCO for Power Reduction. Circuits Syst Signal Process 43, 1339–1365 (2024). https://doi.org/10.1007/s00034-023-02531-y
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DOI: https://doi.org/10.1007/s00034-023-02531-y