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Design and Analysis of 9-mW 25.5–30.7-GHz CMOS Variable-Gain Amplifier Using Body-Floating Gain-and-Noise-Enhancement Technique

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Abstract

We demonstrate a low-power (Pdc) 25.5–30.7 GHz CMOS variable-gain amplifier (VGA). The VGA constitutes a common-source (CS) input stage (M1), followed by current-reused CS gain (M2) and output stages (M3). Transistors M1-M3 adopt the topology of B-to-D with RB, i.e., body terminal is connected to drain via a large resistance RB, for body self-forward-bias and floating (BSFBF). This leads to gain boosting and NF reduction of the VGA at the same Pdc due to larger transconductance gm (because of larger bias current) and smaller bias voltage, and effective suppression of the substrate leakage and noise. Simultaneous input and noise matching are achieved by suitable selection of the size and bias of M1, and the inductance of Lg1 and L1. Analog switch transistor M4 is in parallel with M3 to tune its overdrive (VOV) and drain-source voltage (VDS) for fine tuning of S21. Digital switch transistor M5 (in conjunction with the series coupling capacitance CC and resonant inductance L10) is in parallel with M2 to control its AC VDS for coarse tuning of S21. In the case of M5 being turned-on, the series of CC-M5-L10 is close to a short-circuit (~ 4.6 Ω) at the output node of M2 over the 3-dB gain bandwidth (f3dB) of 18.4–30.7 GHz. This leads to S21 tuning range boosting. Moreover, M4-M5 adopt DTMOS with RB, i.e., body of M4-M5 is connected to gate via RB, for BSFBF to lower the on-state channel resistance (Rch) and increase the off-state Rch. Further S21 tuning range boosting is attained. The VGA consumes 9 mW, and achieves S21 of 15.4 ± 1.5 dB for 18.4–30.7 GHz, tuning range of 29.8 dB (15.5 ~ − 14.3 dB) at 28 GHz, average NF (NFavg) of 2.79 dB for 18–31 GHz, and figure-of-merit (FOM) of 2.24 GHz. The NFavg and FOM are one of the best results ever reported for wideband VGAs/LNAs with Pdc lower than 10 mW. The eminent results of the VGA indicate it is suitable for 28 GHz 5G systems.

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Acknowledgements

The authors are grateful for the support from Taiwan Semiconductor ReseaRch Institute (TSRI) for chip fabrication and measurements.

Funding

This work is supported by the National Science and Technology Council (NSTC) of Taiwan under contract NSTC112-222-E-260–010.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, ROC

    Yo-Sheng Lin & Bo-Shun Chen

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  1. Yo-Sheng Lin
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Contributions

YSL wrote the main manuscript text and prepared all figures and tables. Circuit layout and part of the measurements were done by Bo-Shun Chen. All authors reviewed the manuscript.

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Correspondence to Yo-Sheng Lin.

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Lin, YS., Chen, BS. Design and Analysis of 9-mW 25.5–30.7-GHz CMOS Variable-Gain Amplifier Using Body-Floating Gain-and-Noise-Enhancement Technique. Circuits Syst Signal Process 43, 3355–3375 (2024). https://doi.org/10.1007/s00034-024-02625-1

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