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Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique

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Abstract

This paper proposes a delta-sigma modulator (DSM) for audio band applications with low-area cost and high-resolution performance characteristics. The proposed circuit is implemented by discrete-time switched capacitor circuits. It employs an assisted 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) as the quantizer. Most importantly, it combines and shares the resistive digital-to-analog (DAC) in DSM and SAR ADC. Therefore, it can achieve high-efficiency advantages and reduce the chip layout cost. After all, the chip area is only 0.096 mm2 by the 0.18 um 1P6M CMOS process. It achieves 96 dB dynamic range (DR), 83.1 dB signal to noise and distortion ratio (SNDR), and 93.4 dB signal to noise ratio (SNR) with 25 kHz signal bandwidth and oversampling ratio (OSR) of 64.

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Acknowledgements

This work was supported in part by the National Science and Technology Council, Taiwan, under Grant NSTC 111-2221-E-034-003. The authors would like to thank the supports of Taiwan Semiconductor Research Institute (TSRI) in EDA tool assistance and chip fabrication.

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Hsin-Liang Chen had the idea of the presented paper and written it. Hong-Ming Chiu and Hung-Chi Chang performed the literature search and circuit design works. Hsiao-Hsing Chou and Jen-Shiun Chiang performed system discussion and paper revision.

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Correspondence to Jen-Shiun Chiang.

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Chen, HL., Chou, HH., Chiu, HM. et al. Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique. Circuits Syst Signal Process 44, 2–23 (2025). https://doi.org/10.1007/s00034-024-02832-w

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