Abstract
This paper proposes a delta-sigma modulator (DSM) for audio band applications with low-area cost and high-resolution performance characteristics. The proposed circuit is implemented by discrete-time switched capacitor circuits. It employs an assisted 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) as the quantizer. Most importantly, it combines and shares the resistive digital-to-analog (DAC) in DSM and SAR ADC. Therefore, it can achieve high-efficiency advantages and reduce the chip layout cost. After all, the chip area is only 0.096 mm2 by the 0.18 um 1P6M CMOS process. It achieves 96 dB dynamic range (DR), 83.1 dB signal to noise and distortion ratio (SNDR), and 93.4 dB signal to noise ratio (SNR) with 25 kHz signal bandwidth and oversampling ratio (OSR) of 64.
















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References
S. An, S. Xia, Y. Ma, A. Ghani, C.H. See, R.A. Abd-Alhameed, C. Niu, R. Yang, A Low power sigma-delta modulator with hybrid architecture. Sensors 20(18), 5309 (2020). https://doi.org/10.3390/s20185309
S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, T. S. Fiez, A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multirate VCO-based quantizer, in Custom Integrated Circuits Conference (IEEE, San Jose, CA, USA, 2011), pp. 1–4. https://doi.org/10.1109/CICC.2011.6055290
B.E. Boser, B.A. Wooley, The design of sigma-delta modulation A/D converters. IEEE J. Solid-State Circ. 23(6), 1298–1308 (1988). https://doi.org/10.1109/4.90025
C.-C. Chen, Y.-H. Huang, J.C.J.S. Marquez, C.-C. Hsieh, A 12-ENOB second-order noise-shaping SAR ADC with PVT-insensitive voltage–time–voltage converter. IEEE J. Solid-State Circ. 58(10), 2897–2906 (2023). https://doi.org/10.1109/JSSC.2023.3273311
C. Chen, Z. Tan, M. A. P. Pertijs, A 1V 14b self-timed zero-crossing-based incremental ADC, in IEEE International Solid-State Circuits Conference. Digest of Technical Papers, (IEEE, San Francisco, CA, USA, 2013), pp. 274–275. https://doi.org/10.1109/ISSCC.2013.6487732
J.A. Fredenburg, M.P. Flynn, A 90-MS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC. IEEE J. Solid-State Circ. 47(12), 2898–2904 (2012). https://doi.org/10.1109/JSSC.2012.2217874
X. Guo, R. Chen, Z. Chen, B. Li, A 13b 600–675MS/s tri-state pipelined-SAR ADC with inverter-based open-loop residue amplifier. IEEE J. Solid-State Circ. 58(3), 624–633 (2023). https://doi.org/10.1109/JSSC.2022.3222162
Y. Guo, J. Jin, X. Liu, J. Zhou, An inverter-based continuous time sigma delta ADC with latency-free DAC calibration. IEEE Trans Circ. Syst. I: Regul. Pap. 52(11), 3630–3642 (2020). https://doi.org/10.1109/TCSI.2020.3009652
J.-H. Han, K.-I. Cho, H.-J. Kim, J.-H. Boo, J.S. Kim, G.-C. Ahn, A 96dB dynamic range 2kHz bandwidth 2nd order delta-sigma modulator using modified feedforward architecture with delayed feedback. IEEE Trans Circ. Syst. II: Exp. Brief. 68(5), 1645–1649 (2021). https://doi.org/10.1109/TCSII.2021.3066628
J. He, S. Zhan, D. Chen, R.L. Geiger, Analyses of static and dynamic random offset voltages in dynamic comparators. IEEE Trans Circ. Syst. I: Regul. Pap. 56(5), 911–919 (2009). https://doi.org/10.1109/TCSI.2009.2015207
L. Jie, B. Zheng, H.-W. Chen, M.P. Flynn, A cascaded noise-shaping SAR architecture for robust order extension. IEEE J. Solid-State Circ. 55(12), 3236–3247 (2020). https://doi.org/10.1109/JSSC.2020.3019487
Y.-H. Kim, S. Cho, A 1-GS/s 9-bit zero-crossing-based pipeline ADC using a resistor as a current source. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(7), 2570–2579 (2016). https://doi.org/10.1109/TVLSI.2015.2508564
T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J. Solid-State Circuits 28(4), 523–527 (1993). https://doi.org/10.1109/4.210039
H. Lee, S.P. Aurangozeb, J. Kim, C. Kim, A 6-bit 2.5-GS/s time-interleaved analog-to-digital converter using resistor-array sharing digital-to-analog converter. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(11), 2371–2383 (2015). https://doi.org/10.1109/TVLSI.2014.2372033
S.-Y. Lee, Y.-T. Hsieh, H.-Y. Lee, S.-S. Chang, J.-Y. Chen, A direct current-sensing VCO-based 2nd-order continuous-time sigma-delta modulator for biosensor readout applications. IEEE Trans. Biom. Circ. Syst. 8(2), 3630–3642 (2024). https://doi.org/10.1109/TBCAS.2023.3322901
C. Y. Lee, U.-K. Moon, A 0.0375mm2 203.5μW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS, in IEEE International Solid-State Circuits Conference. Digest of Technical Papers, (IEEE, San Francisco, CA, USA, 2022), pp. 412–414. https://doi.org/10.1109/ISSCC42614.2022.9731606
S. Lee, S. Park, Y. Kim, Y. Kim, J. Lee, J. Lee, Y. Chae, A 0.6-V 86.5-dB DR 40-kHz BW inverter-based continuous-time delta–sigma modulator with PVT-robust body-biasing. IEEE J. Solid-State Circ. Lett. 49(6), 178–181 (2021). https://doi.org/10.1109/LSSC.2021.3119641
J. Lee, S. Song, J. Roh, A 103 dB DR fourth-order delta-sigma modulator for sensor applications. Electronics 8(10), 1093 (2019). https://doi.org/10.3390/electronics8101093
S. Li, N. Sun, A 174.3dB FoM VCO-Based CT ∆Σ Modulator With a Fully Digital Phase Extended Quantizer and Tri-level Resistor DAC in 130nm CMOS, in European Solid-State Device Research Conference (IEEE, Lausanne, Switzerland, 2016), pp. 241–244. https://doi.org/10.1109/ESSCIRC.2016.7598287
H. Luo, Y. Han, R. C.C. Cheung, X. Liu, T. Cao, A 0.8-V 230-μW 98-dB DR inverter-based modulator for audio applications, IEEE J. Solid-State Circ. 48(10), 2430–2441 (2013). https://doi.org/10.1109/JSSC.2013.2275659
H. Maghami, P. Payandehnia, H. Mirzaie, R. Zanbaghi, H. Zareie, J. Goins, S. Dey, K. Mayaram, T.S. Fiez, A highly linear OTA-less 1–1 MASH VCO-based ΔΣ ADC with an efficient phase quantization noise extraction technique. IEEE J. Solid-State Circ. 55(3), 706–718 (2020). https://doi.org/10.1109/JSSC.2019.2954764
D. Marche, Y. Savaria, Modeling R-2R segmented-ladder DACs. IEEE Trans Circ. Syst. I: Regul. Pap. 57(1), 31–43 (2009). https://doi.org/10.1109/TCSI.2009.2019396
F. Michel, M.S.J. Steyaert, A 250 mV 7.5 μW 61 dB SNDR SC modulator using near-threshold-voltage-biased inverter amplifiers in 130 nm CMOS. IEEE J. Solid-State Circ. 47(3), 709–721 (2012). https://doi.org/10.1109/JSSC.2011.2179732
D.-J. Min, J.H. Shim, A charge-sharing-based two-phase charging scheme for zero-crossing-based integrator circuits. Electronics 8(7), 821 (2019). https://doi.org/10.3390/electronics8070821
D.-J. Min, J. H. Shim, A zero-crossing-based integrator with bidirectional two-phase charging and selective-reset operations for ΔΣ ADCs, in International Symposium On Circuits and Systems (IEEE, Daegu, Korea, 2021). https://doi.org/10.1109/ISCAS51556.2021.9401569
B. Murmann, ADC performance survey 1997–2024. https://github.com/bmurmann/ADC-survey (2024).
T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, U.-K. Moon, A 630 μW zero-crossing-based ADC using switched-resistor current sources in 45nm CMOS, in Custom Integrated Circuits Conference (IEEE, San Jose, CA, USA, 2009), pp. 1–4. https://doi.org/10.1109/CICC.2009.5280909
T. Musah, U.-K. Moon, Pseudo-differential zero-crossing-based circuit with differential error suppression, in International Symposium On Circuits and Systems (IEEE, Paris, France, 2010), pp. 1731–1734. https://doi.org/10.1109/ISCAS.2010.5537538
N. Narasimman, T.T.-H. Kim, An ultra-low-voltage VCO-based ΔΣ modulator using self-compensated current reference for variation tolerance. Circuits Syst Signal Process 40, 1089–1110 (2021). https://doi.org/10.1007/s00034-020-01523-6
J.-E. Park, Y.-H. Hwang, D.-K. Jeong, A 0.4-to-1 V voltage scalable ADC with two-step hybrid integrator for IoT sensor applications in 65-nm LP CMOS. IEEE Trans Circ. Syst. II: Exp. Brief. 64(12), 1417–1421 (2017). https://doi.org/10.1109/TCSII.2017.2753841
B. Razavi, The StrongARM latch [a circuit for all seasons]. IEEE Solid-State Circ. Magz. 7(2), 12–17 (2015). https://doi.org/10.1109/MSSC.2015.2418155
R. Schreier, S. Pavan, G.C. Temes, Understanding delta‐sigma data converters (Wiley, 2017). https://doi.org/10.1002/9781119258308
R. Schreier, J. Silva, J. Steensgaard, G.C. Temes, Design-oriented estimation of thermal noise in switched-capacitor circuits. IEEE Trans Circ. Syst. I: Regul. Pap. 52(11), 2358–2368 (2005). https://doi.org/10.1109/TCSI.2005.853909
L. Shi, E. Thaigarajan, R. Singh, E. Hancioglu, U.-K. Moon, G. Temes, Noise-shaping SAR ADC using a two-capacitor digitally calibrated DAC with 85.1 dB DR and 91 dB SFDR, in International Midwest Symposium on Circuits and Systems (IEEE, Springfield, MA, USA, 2020), pp. 353–356. https://doi.org/10.1109/MWSCAS48704.2020.9184516
S.-K. Shin, J.C. Rudell, D.C. Daly, C.E. Muñoz, D.-Y. Chang, K. Gulati, H.-S. Lee, M.Z. Straayer, A 12 bit 200 MS/s zero-crossing-based pipelined ADC with early Sub-ADC decision and output residue background calibration. IEEE J. Solid-State Circ. 49(6), 1366–1382 (2014). https://doi.org/10.1109/JSSC.2014.2322853
U. Sönmez, F. Sebastiano, K.A.A. Makinwa, Analysis and design of VCO-based phase-domain modulators. IEEE Trans Circ. Syst. I: Regul. Pap. 64(5), 1075–1084 (2017). https://doi.org/10.1109/TCSI.2016.2638827
J. Wang, X. Cheng, J. Han, X. Zeng, Synthesizable lead-lag quantization technique for digital VCO-based ∆Σ ADC. Microelectron. J. 110, 105007 (2021). https://doi.org/10.1016/j.mejo.2021.105007
H. Xu, A.A. Abidi, Analysis and design of regenerative comparators for low offset and noise. IEEE Trans Circ. Syst. I: Regul. Pap. 66(8), 2817–2830 (2019). https://doi.org/10.1109/TCSI.2019.2909032
H. Zhuang, W. Guo, J. Liu, H. Tang, Z. Zhu, L. Chen, N. Sun, A second-order noise-shaping SAR ADC with passive integrator and tri-level voting. IEEE J. Solid-State Circ. 54(6), 1636–1647 (2019). https://doi.org/10.1109/JSSC.2019.2900150
Acknowledgements
This work was supported in part by the National Science and Technology Council, Taiwan, under Grant NSTC 111-2221-E-034-003. The authors would like to thank the supports of Taiwan Semiconductor Research Institute (TSRI) in EDA tool assistance and chip fabrication.
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Hsin-Liang Chen had the idea of the presented paper and written it. Hong-Ming Chiu and Hung-Chi Chang performed the literature search and circuit design works. Hsiao-Hsing Chou and Jen-Shiun Chiang performed system discussion and paper revision.
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Chen, HL., Chou, HH., Chiu, HM. et al. Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique. Circuits Syst Signal Process 44, 2–23 (2025). https://doi.org/10.1007/s00034-024-02832-w
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DOI: https://doi.org/10.1007/s00034-024-02832-w