Abstract
We present translational lemmas for the three standard models of parallel computation, and apply them to obtain tight hierarchy results. It is shown that, for arbitrarily small rational constant \(\epsilon > 0\) , (i) there is a language which can be accepted by a \(U_{\rm E}\) -uniform circuit family of depth \(c(1+\epsilon)(\log n)^{r_1}\) and size \(dn^{r_2(1+\epsilon)}\) but not by any \(U_{\rm E}\) -uniform circuit family of depth \(c(\log n)^{r_1}\) and size \(dn^{r_2}\) , (ii) there is a language which can be accepted by a \(c(9+\epsilon)(\log n)^{r_1}\) -time \(d(4+\epsilon)\log n\)-space ATM with l worktapes but not by any \(c(\log n)^{r_1}\) -time \(d\log n\) -space ATM with the same l worktapes if the number of tape symbols is fixed, and (iii) there is a language which can be accepted by a \(c(1+\epsilon)(\log n)^{r_1}\) -time PRAM with \(dn^{r_2(1+\epsilon)}\) processors but not by any \(c(\log n)^{r_1}\) -time PRAM with \(dn^{r_2}\) processors. Here, c > 0, d ≥ 1, r 1 > 1, and r 2 ≥ 1 are arbitrary rational constants, and l ≥ 2 is an arbitrary integer.
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Preliminary versions of different parts of this paper appeared in Proc. MCU 2004 (LNCS 3354) and Proc. FCT 2005 (LNCS 3623).
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Iwamoto, C., Hatayama, N., Nakashiba, Y. et al. Translational lemmas for DLOGTIME-uniform circuits, alternating TMs, and PRAMs. Acta Informatica 44, 345–359 (2007). https://doi.org/10.1007/s00236-007-0051-2
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DOI: https://doi.org/10.1007/s00236-007-0051-2