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Correct hardware synthesis

An algebraic approach

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Abstract

This paper presents an algebraic compilation approach to the correct synthesis (compilation into hardware) of a synchronous language with shared variables and parallelism. The synthesis process generates a hardware component that implements the source program by means of gradually reducing it into a highly parallel state-machine. The correctness of the compiler follows by construction from the correctness of the transformations involved in the synthesis process. Each transformation is proved sound from more basic algebraic laws of the source language; the laws are themselves formally derived from a denotational semantics expressed in the Unified Theories of Programming. The proposed approach is based on previous efforts that handle both software and hardware compilation, in a pure algebraic style, but the complexity of our source language demanded significant adaptations and extensions to the existing approaches.

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Authors and Affiliations

  1. Computer Science Department, The University of York, York, UK

    Juan Perna & Jim Woodcock

  2. Centro de Informatica, Universidade Federal de Pernambuco, Recife, Brazil

    Augusto Sampaio & Juliano Iyoda

Authors
  1. Juan Perna
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  2. Jim Woodcock
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  3. Augusto Sampaio
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  4. Juliano Iyoda
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Correspondence to Juan Perna.

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Perna, J., Woodcock, J., Sampaio, A. et al. Correct hardware synthesis. Acta Informatica 48, 363–396 (2011). https://doi.org/10.1007/s00236-011-0142-y

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