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FPGA-orthopoly: a hardware implementation of orthogonal polynomials

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Abstract

There are many algorithms based on orthogonal functions that can be applied to real-world problems. For example, many of them can be reduced to approximate the solution of a dynamical system, and the approximation can be done with orthogonal functions. But calculating the orthogonal functions is very time-consuming, there are many difficulties in implementation of them and because of these drawbacks, they are not utilized in real applications. For the purpose of solving this issue and filling the gap between the theory and real applications, in this paper, an FPGA implementation of some classical orthogonal polynomials families is presented. Here, hardware architectures of the first and second kinds of Chebyshev, Jacobi, Legendre, Gegenbauer, Laguerre, and Hermit polynomials are presented. The experiments show that the presented architectures are low power, fast, and with a small circuit area. The obtained results show a 10.5\(\times\) speed-up in the best case, 1.5\(\times\) speed-up in the worst case, and at least 47% reduction in power consumption in comparison with the state-of-the-art hardware implementations. All implementations and codes are available at https://github.com/sampp098/forthopoly.

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Authors and Affiliations

  1. School of Computer Science, Institute for Research in Fundamental Sciences, Farmanieh Campus, Tehran, Iran

    M. Asghari & A. H. Hadian Rasanan

  2. Institute for Cognitive and Brain Sciences, Shahid Beheshti University, G.C., Tehran, Iran

    A. H. Hadian Rasanan & K. Parand

  3. Department of Electrical Engineering and Information Technology, Iranian Research Organization for Science and Technology (IROST), Tehran, Iran

    S. Gorgin

  4. Department of Computer Engineering, Chosun University, Gwangju, Republic of Korea

    S. Gorgin

  5. Faculty of Computer Science and Engineering, Shahid Beheshti University, G.C., Tehran, Iran

    D. Rahmati

  6. Department of Computer and Data Science, Faculty of Mathematics, Shahid Beheshti University, G.C., Tehran, Iran

    K. Parand

  7. Department of Statistics and Actuarial Science, University of Waterloo, Waterloo, Canada

    K. Parand

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  1. M. Asghari
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  2. A. H. Hadian Rasanan
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Correspondence to A. H. Hadian Rasanan.

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Appendices

Appendix 1

See Table 7.

Table 7 Table of the coefficients in the BCS algorithm [39]
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Appendix 2

See Fig. 14.

Fig. 14
figure 14

The implemented design of the OPPU for Chebyshev1 on the ZTurn 7020 FPGA board

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Asghari, M., Hadian Rasanan, A.H., Gorgin, S. et al. FPGA-orthopoly: a hardware implementation of orthogonal polynomials. Engineering with Computers 39, 2257–2276 (2023). https://doi.org/10.1007/s00366-022-01612-x

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