Negation-Limited Complexity of Parity and Inverters

Abstract

In negation-limited complexity, one considers circuits with a limited number of NOT gates, being motivated by the gap in our understanding of monotone versus general circuit complexity, and hoping to better understand the power of NOT gates. We give improved lower bounds for the size (the number of AND/OR/NOT) of negation-limited circuits computing Parity and for the size of negation-limited inverters. An inverter is a circuit with inputs x ₁,…,x _n and outputs ¬ x ₁,…,¬ x _n . We show that: (a) for n=2^r−1, circuits computing Parity with r−1 NOT gates have size at least 6n−log ₂(n+1)−O(1), and (b) for n=2^r−1, inverters with r NOT gates have size at least 8n−log ₂(n+1)−O(1). We derive our bounds above by considering the minimum size of a circuit with at most r NOT gates that computes Parity for sorted inputs x ₁≥⋅⋅⋅≥x _n . For an arbitrary r, we completely determine the minimum size. It is 2n−r−2 for odd n and 2n−r−1 for even n for ⌈log ₂(n+1)⌉−1≤r≤n/2, and it is ⌊3n/2⌋−1 for r≥n/2. We also determine the minimum size of an inverter for sorted inputs with at most r NOT gates. It is 4n−3r for ⌈log ₂(n+1)⌉≤r≤n. In particular, the negation-limited inverter for sorted inputs due to Fischer, which is a core component in all the known constructions of negation-limited inverters, is shown to have the minimum possible size. Our fairly simple lower bound proofs use gate elimination arguments in a somewhat novel way.