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Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

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Abstract

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.

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References

  1. Vuckovic A, Radivojevic V, Chen AC, Popovic D (2002) Automatic recognition of alertness and drowsiness from EEG by an artificial neural network. Med Eng Phys 24(5):349–360. doi:10.1016/S1350-4533(02)00030-9

    Article  Google Scholar 

  2. Ben Khalifa K, Bedoui MH, Dogui M, Alexandre F (2004) Analysis of vigilance states by neural networks. Proc ICTTA 2004, pp 429–430. doi:10.1109/ICTTA.2004.1307815

  3. Nakamoto T, Ozawa T, Shibata Y (2003) Improvement of odor recognition chip. Proc IEEE sensors, pp 1203–1208. doi:10.1109/ICSENS.2003.1279136

  4. Kugler M, Lopes M (2007) A configware approach for the implementation of a LVQ neural network. Int J Comput Intell Res 3(1):21–25

    Google Scholar 

  5. Ben Khalifa K, Girau B, Alexandre F, Bedoui MH (2004) Parallel FPGA implementation of self-organizing maps. Proc ICM 2004, pp 709–712. doi:10.1109/ICM.2004.1434765

  6. Curcio G, Casagrande M, Bertini M (2001) Sleepiness: evaluating and quantifying methods. Int J Psychophysiol 41(3):251–263. doi:10.1016/S0167-8760(01)00138-6

    Article  Google Scholar 

  7. Kerkeni N, Alexandre F, Bedoui MH, Bougrain L, Dogui M (2005) Neuronal spectral analysis of EEG and expert knowledge integration for automatic classification of sleep stages. In: WSEAS transactions on information science and applications 11(2):1854–1861

  8. Grandpierre T, Sorel Y (2003) From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow graphs transformations. Proc MEMCODE 2003, pp 123–133. doi:10.1109/MEMCOD.2003.1210097

  9. Kaouane L, Akil M, Sorel Y, Grandpierre T (2004) A methodology to implement real-time applications onto reconfigurable devices. J Supercomput 30(3):283–301. doi:10.1023/B:SUPE.0000045213.82276.8e

    Article  Google Scholar 

  10. Kohonen T (2001) Self-organizing maps. Springer, Berlin. ISBN: 3-540-67921-9, ISSN: 0720-678X

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Author information

Authors and Affiliations

  1. Team TIM, Laboratory of Biophysics, Faculty of Medicine of Monastir, Monastir, 5019, Tunisia

    Mohamed Boubaker, Khaled Ben Khalifa & Mohamed Hedi Bedoui

  2. Laboratoire d’Informatique Gaspard-Monge, Equipe A3SI, ESIEE Paris, Université Paris-Est, Cité Descartes, 2 boulevard Blaise Pascal, BP 99, 93162, Noisy Le Grand Cedex, France

    Mohamed Akil & Thierry Grandpierre

Authors
  1. Mohamed Boubaker
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  2. Mohamed Akil
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  3. Khaled Ben Khalifa
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  4. Thierry Grandpierre
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  5. Mohamed Hedi Bedoui
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Corresponding author

Correspondence to Mohamed Boubaker.

Appendices

Appendix 1: Tool of SynDEx-IC design implemented to the LVQ implementation

Figure 8 describes the graphic interface of the CAD software at the level system SynDEx-IC. This IHM developed in Tcl/Tk allows the user to specify its algorithm: specification of the operations, the input formats and the algorithm description. This specification is hierarchical.

Fig. 8
figure 8

Graphical user interface of the SynDEx-IC software

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Figure 8 shows SynDEx-IC graphic interface. As illustrated in this figure, the use of the interface allows the user to:

  • Characterize the nodes of its algorithm according to selected FPGA device.

  • Indicate the constraint of latency of this implementation.

  • Launch the heuristics:

    • display the various results of the exploration neighborhood graphs (see Fig. 9),

      Fig. 9
      figure 9

      The LVQ neighborhood graph corresponding to a defactorization by two of frontier FF2

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    • estimation results: consumed resources and latency of each solution (defactorization).

  • Launch the automatic generation of synthesizable VHDL code of each solution.

  • Visualize the generated code.

Table 5 describes the results obtained from this neighborhood graph.

Table 5 Results obtained from LVQ neighborhood graph corresponding to a defactorization by two of frontier FF2
Full size table

Appendix 2: Success rates of various LVQ configurations

In Table 6, we report the results for various LVQ configurations in two subjects (the number of inputs in the first layer, 12 or 23 and the number of neurons on the competition layer, 3 × 3, 4 × 4, 5 × 5, 6 × 6 or 7 × 7). For subject 1, we obtained the best total validation success rate (TVSR) at 100% for all the 3 × 3, 4 × 4, 5 × 5, 6 × 6 and 7 × 7 with the 23 inputs. For subject 2, the best (TVSR) was at 91% with 7 × 7 neurones in the competition layer and 23 inputs.

Table 6 Success rates of various LVQ configurations for two subjects
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Based on the approach reported in [2], our study shows how important it is to adapt the neural network architecture (input and competitive layers) to the subject.

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Boubaker, M., Akil, M., Ben Khalifa, K. et al. Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices. Neural Comput & Applic 19, 283–297 (2010). https://doi.org/10.1007/s00521-009-0296-5

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  • DOI: https://doi.org/10.1007/s00521-009-0296-5

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