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Circuit design completion using graph neural networks

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Abstract

Electronic design automation tools are widely used in circuit design and greatly assist designers in handling the complexities and challenges of circuit design and evaluation. There have been numerous recent developments in using machine learning tools, particularly graph neural networks (GNNs), to address circuit design problems. These techniques take advantage of the natural representation of a circuit as a graph. In this study, we propose using state-of-the-art GNNs to solve a key circuit design issue. Specifically, we are interested in addressing the circuit completion problem (CCP), where the goal is to determine the missing components and their connections in a partially designed or evaluated circuit. We provide a novel two-step solution to this problem: First, we formulate missing component identification as a graph classification task in the graph-based representation of partial circuit, and second, we treat the placement and connectivity of the newly (predicted) component as a link completion problem. We propose a novel graph learning framework called feature-enhanced graph isomorphism network that combines both GNNs and graph descriptors in an end-to-end fashion to extract expressive graph representations. We also present three new circuit datasets to implement and test our solutions. Our extensive experiments demonstrate that the proposed framework is an effective and generalizable solution to the CCP problem.

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Data availability statement

The datasets generated during and/or analyzed during the current study are available in the spice-datasets repository, https://github.com/symbench/spice-datasets.

Code availability

The source code and preprocessed data for the experiments are available in the Circuit-Completion-Using-GNNs repository, https://github.com/Anwar-Said/Circuit-Completion-Using-GNNs

Notes

  1. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html.

  2. https://www.kicad.org/.

  3. https://github.com/symbench/spice-datasets.

  4. https://github.com/Anwar-Said/Circuit-Completion-Using-GNNs.

  5. https://github.com/symbench/spice-datasets.

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Acknowledgements

This work is supported in part by DARPA through contract number FA8750-20-C-0537. Any opinions, findings, and conclusions or recommendations expressed are those of the authors and do not necessarily reflect the views of the sponsor.

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Authors and Affiliations

  1. Department of Computer Science, Vanderbilt University, Nashville, 37235, TN, USA

    Anwar Said, Mudassir Shabbir, Brian Broll, Peter Völgyesi & Xenofon Koutsoukos

  2. Department of Systems Engineering, University of Texas at Dallas, Texas, 75080, TX, USA

    Waseem Abbas

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Correspondence to Mudassir Shabbir.

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Said, A., Shabbir, M., Broll, B. et al. Circuit design completion using graph neural networks. Neural Comput & Applic 35, 12145–12157 (2023). https://doi.org/10.1007/s00521-023-08346-x

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