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ParVec: vectorizing the PARSEC benchmark suite

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Abstract

Energy efficiency has recently replaced performance as the main design goal for microprocessors across all market segments. Vectorization, parallelization, specialization and heterogeneity are the key approaches that both academia and industry embrace to make energy efficiency a reality. New architectural proposals are validated against real applications in order to ensure correctness and perform performance and energy evaluations. However, keeping up with architectural changes while maintaining similar workloads and algorithms (for comparative purposes) becomes a real challenge. If benchmarks are optimized for certain features and not for others, architects may end up overestimating the impact of certain techniques and underestimating others. The main contribution of this work is a detailed description and evaluation of ParVec, a vectorized version of the PARSEC benchmark suite (as a case study of a commonly used application set). ParVec can target SSE, AVX and NEON™ SIMD architectures by means of custom vectorization and math libraries. The performance and energy efficiency improvements from vectorization depend greatly on the fraction of code that can be vectorized. Vectorization-friendly benchmarks obtain up to 10\(\times \) energy improvements per thread. The ParVec benchmark suite is available for the research community to serve as a new baseline for evaluation of future computer systems.

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Notes

  1. This happens in applications with data dependencies, idle cycles and average IPC. If a “power/performance virus” kernel is used, SIMD units will burn additional power depending on register size.

  2. Model Specific Registers.

  3. http://embree.github.io/.

  4. Region of Interest, that is, code without IO.

    Fig. 2
    figure 2

    Blackscholes (from left to right) runtime, cache miss rate and energy (Intel)

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    Fig. 3
    figure 3

    Blackscholes (from left to right) runtime, cache miss rate and energy (ARM)

    Full size image

  5. Sum of the horizontal and vertical components.

  6. A stride load of size \(n\) will require \(n\) registers as input in addition to the memory address to load from. Data is converted from AoS to SoA and stored into the target registers.

  7. In financial terms, an option granting its owner the right but not the obligation to enter into an underlying swap.

  8. http://code.entropywave.com/orc/.

  9. A manual loop unrolling mechanism.

  10. http://www.videolan.org/developers/x264.html.

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Acknowledgments

The authors would like to thank the Computer Architecture and Design (CARD) group. The Energy Efficient Computing Systems (EECS) for the funding, Intel for providing the hardware to be used in our experiments and ARM for their constant support to our group.

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Authors and Affiliations

  1. Department of Computer and Information Science (IDI), NTNU, 7491, Trondheim, Norway

    Juan M. Cebrian, Magnus Jahre & Lasse Natvig

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  1. Juan M. Cebrian
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  2. Magnus Jahre
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  3. Lasse Natvig
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Correspondence to Juan M. Cebrian.

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Cebrian, J.M., Jahre, M. & Natvig, L. ParVec: vectorizing the PARSEC benchmark suite. Computing 97, 1077–1100 (2015). https://doi.org/10.1007/s00607-015-0444-y

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