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Generation of parallel synchronization-free tiled code

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Abstract

A novel approach to generation of parallel synchronization-free tiled code for the loop nest is presented. It is derived via a combination of the Polyhedral and Iteration Space Slicing frameworks. It uses the transitive closure of loop nest dependence graphs to carry out corrections of original rectangular tiles so that all dependences of the original loop nest are preserved under the lexicographic order of target (corrected) tiles. Then parallel synchronization-free tiled code is generated on the basis of valid (corrected) tiles applying the transitive closure of dependence graphs. The main contribution of the paper is demonstrating that the presented technique is able to generate parallel synchronization-free tiled code, provided that the exact transitive closure of a dependence graph can be calculated and there exist synchronization-free slices on the statement instance level in the loop nest. We show that the presented approach extracts such a parallelism when well-known techniques fail to extract it. Enlarging the scope of loop nests, for which synchronization-free tiled code can be generated, is achieved by means of applying the intersection of extracted slices and generated valid tiles, in contrast to forming slices of valid tiles as suggested in previously published techniques based on the transitive closure of a dependence graph. The presented approach is implemented in the publicly available TC optimizing compiler. Results of experiments demonstrating the effectiveness of the approach and the efficiency of parallel programs generated by means of it are discussed.

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Notes

  1. If a slice has multiple sources, then although all its sources belong to \({ UDS}\), only the lexicographically minimal source is the representative of a slice.

  2. http://tc-optimizer.sourceforge.net.

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Authors and Affiliations

  1. Faculty of Computer Science, West Pomeranian University of Technology, ul. Zolnierska 49, 71-210, Szczecin, Poland

    Wlodzimierz Bielecki, Marek Palkowski & Piotr Skotnicki

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  1. Wlodzimierz Bielecki
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  2. Marek Palkowski
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  3. Piotr Skotnicki
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Correspondence to Piotr Skotnicki.

Appendix A: Tile correction for arbitrarily nested parametric affine loops

Appendix A: Tile correction for arbitrarily nested parametric affine loops

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Bielecki, W., Palkowski, M. & Skotnicki, P. Generation of parallel synchronization-free tiled code. Computing 100, 277–302 (2018). https://doi.org/10.1007/s00607-017-0576-3

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