Abstract
Observing the timing properties of actual software provides information not derivable from pure modelling of the hardware, software and test data. Equally, modelling provides worst-case timing values that cannot be realistically determined from only testing and measurement. From this observation, we develop a combined methodology, where measured and modelled results are used in turn to build a complete, unified approach to software timing analysis. Beyond this, we develop toward a powerful and symbiotic process, where that data can be freely and reliably exchanged, and that is greater than the obvious sum of the parts.

















Similar content being viewed by others
Notes
A basic block is a sequence of instructions with exactly one entry point at the start and one exit point at the end. The computation time for a basic block is therefore independent of software conditional branches and is determined entirely by hardware features.
The halting problem is an undecidable problem that would have to be solved by a tool that could perform arbitrary timing analysis. Therefore no such tool can exist.
The need for rational values arises when times are driven by more than one different digital clock. For example, a CPU may run at 100 MHz and receive interrupts from one external device clocked at 60 MHz and another clocked at 5.4 MHz. After whole numbers of clock ticks on diverse clocks have been scaled to make them compatible, the results are not always exactly expressible as a decimal. Rounding will generally be applied at some stage in timing analysis but at least no information is lost in the ATF transfer.
References
Betts, A., Merriam, N., Bernat, G.: Hybrid measurement-based WCET analysis at the source level using object-level traces. In: Lisper, B. (ed.) Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010). OpenAccess Series in Informatics (OASIcs), vol. 15, pp. 54–63. Dagstuhl, Germany (2010). Schloss Dagstuhl—Leibniz-Zentrum fuer Informatik. The printed version of the WCET’10 proceedings are published by OCG (http://www.ocg.at). ISBN 978-3-85403-268-7
Ferdinand, C., Heckmann, R.: aiT: worst-case execution time prediction by static programm analysis. In: Jacquart, R. (ed.) Building the Information Society. IFIP 18th World Computer Congress, Topical Sessions, Toulouse, France, 22–27 August 2004, pp. 377–384. Kluwer, Dordrecht (2004)
MPC565 Reference Manual. Freescale Semiconductor (2005). http://www.freescale.com
Gustafsson, J., Ermedahl, A., Sandberg, C., Lisper, B.: Automatic derivation of loop bounds and infeasible paths for WCET analysis using abstract execution. In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS’06), Rio de Janeiro, Brazil, pp. 57–66. IEEE Computer Society, New York (2006)
Gustafsson, J., Lisper, B., Schordan, M., Ferdinand, C., Gliwa, P., Jersak, M., Bernat, G.: ALL-TIMES—a European project on integrating timing technology. In: Proceedings of the 3rd International Symposium on Leveraging Applications of Formal Methods (ISOLA’08), Porto Sani, Greece. CCIS, vol. 17, pp. 445–459. Springer, Berlin (2008)
Henia, R., Hamann, A., Jersak, M., Racu, R., Richter, K., Ernst, R.: System level performance analysis—the SymTA/S approach. IEEE Proc. Comput. Digit. Tech. 152(2), 148–166 (2005)
Lisper, B.: The ALL-TIMES project: introduction and overview (2012, this volume)
Merriam, N., Lisper, B.: Estimation of productivity increase for timing analysis tool chains (2012, this volume)
Schordan, M.: Combining tools and languages for static analysis and optimization of high-level abstractions. Technical report, TU Vienna, Austria (2007)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Merriam, N., Gliwa, P. & Broster, I. Measurement and tracing methods for timing analysis. Int J Softw Tools Technol Transfer 15, 9–28 (2013). https://doi.org/10.1007/s10009-012-0266-6
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10009-012-0266-6