Abstract
Static worst-case timing analyses compute safe timing bounds of applications running in real-time systems. These bounds are necessary to evaluate the strict timing constraints of real-time systems. Moreover, the inherent complexity of such systems demands that their timing analyses are able to cope with the large resulting state space. In this direction, a potential solution is to perform compositional timing analysis, where the system-level timing is obtained from component-level timings. Undesired timing phenomena, called timing anomalies, threaten the soundness of (compositional) timing analyses. In this work, we investigate how the industrial superscalar TriCore architecture is amenable for compositional timing analyses via a formal evaluation of amplification timing anomalies. Firstly, we adapt and extend a specialized abstraction, called canonical pipeline model, to capture the amplification effects in a formal model of the TriCore architecture. Then, we use model checking to efficiently detect amplification timing anomalies and report the associated complexity results. Finally, we aim for better precision as we design and implement counterexample-based methods so as to uncover patterns leading to such anomalies.
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Notes
In this paper, we note an interpretation for which a formula is true an SMT model to distinguish it from our pipeline models.
It cannot interfere with the up.I instruction since both instructions may only access the PMI in the IF stage.
For instance, the memdep attribute globally characterizes two instructions.
This delay \(delay\_dw\) is here actually a tuple (one delay per I or LS downstream instruction) and a positive delay value is a tuple different from the \(null\_delay=(0,0)\).
With the only-upstream progression logic however (see Sect. 7.1.1).
Just before the EX stage where the SRI bus access will occur through the DMI (Sect. 5.2).
Note that the converse is not true, as mentioned above.
Namely, the same scenario if we omit the pipeline stages that are not responsible for the delay scenario.
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Binder, B., Asavoae, M., Brandner, F. et al. Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture. Int J Softw Tools Technol Transfer 24, 415–440 (2022). https://doi.org/10.1007/s10009-022-00655-1
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DOI: https://doi.org/10.1007/s10009-022-00655-1