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Modeling and formal analysis of virtually synchronous cyber-physical systems in AADL

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Abstract

This paper presents the HybridSynchAADL modeling language and formal analysis tool for virtually synchronous cyber-physical systems with complex control programs, continuous behaviors, and bounded clock skews, network delays, and execution times. We leverage the Hybrid PALS methodology, so that it is sufficient to model and verify the much simpler underlying synchronous designs. We define the HybridSynchAADL language as a sublanguage of the avionics modeling standard AADL for modeling such synchronous designs in AADL. We define the formal semantics of HybridSynchAADL using Maude with SMT solving, which allows us to represent advanced control programs and communication features in Maude, while capturing timing uncertainties and continuous behaviors symbolically with SMT solving. We have developed new general methods for optimizing the performance of such symbolic rewriting, which makes the analysis of HybridSynchAADL models feasible. We have integrated the formal modeling and analysis of HybridSynchAADL models into the OSATE tool environment for AADL. Finally, we demonstrate the effectiveness of the Hybrid PALS methodology and HybridSynchAADL on a number of applications, including autonomous drones that collaborate to achieve common goals, and compare the performance of our tool with other state-of-the-art formal tools for hybrid systems.

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Notes

  1. If, in addition, all message delays are 0, then the asynchronous system has more than 3 million reachable states, and its model checking takes more than 30 minutes.

  2. Although we present HybridSynchAADL in the context of Hybrid PALS, our language and tool can more generally be used to model and formally analyze any “synchronous” CPSs with continuous local environments that are sampled/actuated based on imprecise local clocks.

  3. Given performance bounds \(\Gamma \), PALS can find the shortest period p that allows all nodes to read the messages in the correct “rounds.”

  4. https://osate.org/

  5. Hardware components include: processor components that schedule and execute threads, memory components, device components, and bus components that interconnect processors, memory, and devices.

  6. A rewrite condition \(t_j \longrightarrow t_j'\) holds if (a substitution instance of) \(t_j'\) is reachable from (the substitution instance of) \(t_j\) in zero or more steps.

  7. There exist specialized solvers to support SMT solving with ODEs [35]. Because they have not been integrated with Maude, the current version only supports continuous functions.

  8. A component path is given by a period-separated path of component identifiers in AADL; for example,

    figure pg
  9. Since the period of the system is 10 (ms), we search for states reachable within \(30/10=3\) iterations/steps of the system.

  10. We have developed a variety of HybridSynchAADL models for rendezvous and formation control of different numbers of drones with single-integrator and double-integrator dynamics. All of them are available at https://hybridsynchaadl.github.io.

  11. We use equivalent control logic for both HybridSynchAADL models and hybrid automata models. For the drone rendezvous models, the control logics used in this experiment are simplified from one presented in Sect. 8.

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Acknowledgements

We are grateful to John Hatcliff and the anonymous reviewers for very helpful comments on an earlier version of this paper. This work was partly supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2021R1A5A1021944) and Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2022-0-00103).

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Lee, J., Bae, K., Ölveczky, P.C. et al. Modeling and formal analysis of virtually synchronous cyber-physical systems in AADL. Int J Softw Tools Technol Transfer 24, 911–948 (2022). https://doi.org/10.1007/s10009-022-00665-z

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