Verification of arithmetic circuits using binary moment diagrams

Abstract.

Binary moment diagrams (BMDs) provide a canonical representation for linear functions similar to the way binary decision diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word-level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs, have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions as a special case. We propose a hierarchical approach to verifying arithmetic circuits, where component modules are first shown to implement their word-level specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the word-level circuit specification. Multipliers with word sizes of up to 256 bits have been verified by this technique.