Skip to main content
Springer Nature Link
Log in

A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing

  • Original Article
  • Published:
Artificial Life and Robotics Aims and scope Submit manuscript

Abstract

Introduction

Multiply-accumulate operation is the most fundamental operation in digital signal processing for image processing, robotics and automatic control. In this paper, a novel architecture of dynamically reconfigurable fused multiply-adder (FMA) is proposed.

Methods

Dynamic reconfiguration is a method that can change the circuit configuration without stop of operation. The proposed circuit provides the following four calculation modes by dynamic reconfiguration: (1) complex number FMA mode, (2) real number FMA mode, (3) complex number parallel calculation mode, and (4) real number parallel calculation mode.  The data format is single precision floating point format based on IEEE754. The proposed circuit was designed using Verilog-HDL. It was simulated by logic circuit simulator, and implemented on FPGA.

Result

As a result of circuit synthesis, we confirmed the reduction of resource in the proposed circuit. Furthermore, we confirmed proper result for each calculation mode by logic simulation and experiment on FPGA.

Conclusion

The proposed circuit provides the four calculation modes by dynamic reconfiguration. We confirmed the reduction of resource and proper result for each calculation mode.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

Explore related subjects

Discover the latest articles, news and stories from top researchers in related subjects.

References

  1. Todman TJ, Constantinides GA, Wilton SJE, Mencer O, Luk W, Cheung PYK (2005) Reconfigurable computing : architectures and design methods. IEEE Proc Comput Digit Tech 152(2):193–207

    Article  Google Scholar 

  2. Huang L, Ma S, Shen L, Wang Z, Xiao N (2012) Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support. IEEE Trans. Comput 61(5):745–751

    Article  MathSciNet  Google Scholar 

  3. Qi Z, Guo Q, Zhang G, Li X, Hu W (2010) Design of low-cost high-performance floating-point fused multiply-add with reduced power. In: Proceedings of the International Conference on VLSI Design (23rd edn), pp 206–211

  4. Gök M, Özbilen MM (2008) Multi-functional floating-point MAF designs with dot product support. Microelectron J 39:30–40

    Article  Google Scholar 

Download references

Acknowledgments

This work was supported by Tokyo Denki University Science Promotion Fund (QI2J-03).

Author information

Authors and Affiliations

  1. Graduate School of Advanced Science and Technology, Tokyo Denki University, 5 Senju-Asahi-cho, Adachi-ku, Tokyo, 120-8551, Japan

    Akihiko Tsukahara & Akinori Kanasugi

Authors
  1. Akihiko Tsukahara
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. Akinori Kanasugi
    View author publications

    You can also search for this author inPubMed Google Scholar

Corresponding author

Correspondence to Akinori Kanasugi.

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Tsukahara, A., Kanasugi, A. A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing. Artif Life Robotics 19, 233–238 (2014). https://doi.org/10.1007/s10015-014-0162-0

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10015-014-0162-0

Keywords