Abstract
In this paper, we study the problem of joint placement and routing, both in the deterministic and stochastic cases, arising in the field of compilation of dataflow applications for manycore architectures. A GRASP algorithm is first proposed for solving the deterministic version and extended afterwards to treat the chance-constrained program with uncertainty affecting the weights of a dataflow process network. Extensive computational results, on representative synthetic benchmark and real data, illustrate the practical relevance of the approach, as well as the robustness of the obtained stochastic solutions.
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Notes
Despite the exponential growth of the number of transistors which can be placed on an integrated circuit (according to Moore’s law), the performance of practical computing systems does not follow the same growth rate.
Tasks Graph for Free: http://ziyang.eecs.umich.edu/~dickrp/tgff/.
References
Aubry P, Beaucamps PE, Blanc F, Bodin B, Carpov S, Cudennec L, David V, Dore P, Dubrulle P, Dupont BdD, Galea F, Goubier T, Harrand M, Jones S, Lesage J, Louise S, Chaisemartin N, Nguyen T, Raynaud H, Sirdey R (2013) Extended cyclostatic dataflow program compilation and execution for an integrated manycore processor. In: Proceedings of the first international workshop on architecture, languages, compilation and hardware support for emerging manycore systems (ALCHEMY 2013), Barcelona, Spain, pp 1624–1633
Bonfietti A, Benini L, Lombardi M, Milano M (2010) An efficient and complete approach for throughput-maximal sdf allocation and scheduling on multi-core platforms. In: Proceedings of the conference on design, automation and test in Europe, DATE ’10. European Design and Automation Association, pp 897–902
Calafiore G, Campi M (2006) The scenario approach to robust control design. IEEE Trans Autom Control 51(5):742–753
Carpov S, Cudennec L, Sirdey R (2013) Throughput constrained parallelism reduction in cyclo-static dataflow applications. Procedia Comput Sci 18:30–39
Castrillon J, Tretter A, Leupers R, Ascheid G (2012) Communication-aware mapping of KPN applications onto heterogeneous mpsocs. In: Proceedings of the 49th annual design automation conference, DAC ’12. ACM, New York, NY, pp 1266–1271
Choi J, Oh H, Kim S, Ha S (2012) Executing synchronous dataflow graphs on a SPM-based multicore architecture. In: Proceedings of the 49th annual design automation conference, DAC ’12. ACM, New York, NY, pp 664–671
Dupont de Dinechin B, Guironnet de Massas G, Lager G, Léger C, Orgogozo B, Reybert J, Strudel T (2013) A distributed run-time environment for the Kalray MPPA-256 integrated manycore processor. Procedia Comput Sci 18(0):1654–1663
Feo T, Resende M (1995) Greedy randomized adaptive search procedures (GRASP). J Glob Optim 6:109–133
Galea F, Sirdey R (2012) A parallel simulated annealing approach for the mapping of large process networks. In: IPDPS Workshop, pp 1787–1792
Garey M, Johnson D, Stockmeyer L (1976) Some simplified NP-complete graph problems. Theor Comput Sci 1(3):237–267
Goubier T, Sirdey R, Louise S, David V (2011) \(\Sigma \)C: a programming model and langage for embedded manycores. In: Lecture Notes in Computer Science, vol 7016, pp 385–394
Hu J, Marculescu R (2005) Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aided Des Integr Circuits Syst 24(4):551–562
Korte B, Vygen J (2006) Combinatorial optimization: theory and algorithms, 3rd edn. Springer, Berlin
Lee E, Parks T (1995) Dataflow process networks. Proc IEEE 83(5):773–801
Lo VM (1988) Heuristic algorithms for task assignment in distributed systems. IEEE Trans Comput 37(11):1384–1397
Lombardi M, Milano M, Ruggiero M, Benini L (2010) Stochastic allocation and scheduling for conditional task graphs in multiprocessor systems-on-chip. J Sched 13:315–345
Manolache S, Eles P, Peng Z (2008) Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints. ACM Trans Embed Comput Syst 7(2):19:1–19:35
Marcon C, Borin A, Susin A, Carro L, Wagner F (2005) Time and energy efficient mapping of embedded applications onto NoCs. In: ASP-DAC 2005, vol 1, pp 33–38
Marculescu R, Ogras U, Peh LS, Jerger N, Hoskote Y (2009) Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans Comput Aided Des Integr Circuits Syst 28(1):3–21
Marwedel P, Teich J, Kouveli G, Bacivarov I, Thiele L, Ha S, Lee C, Xu Q, Huang L (2011) Mapping of applications to MPSoCs. In: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS ’11. ACM, New York, NY, pp 109–118
Murali S, Benini L, De Micheli G (2006) A methodology for mapping multiple use-cases onto networks on Chips. In: DATE. IEEE, pp 118–123
Orsila H, Salminen E, Hämäläinen TD (2009) Parameterizing simulated annealing for distributing Kahn process networks on multiprocessor SoCs. In: Proceedings of the 11th international conference on System-on-chip, SOC’09, pp 19–26
Prékopa A (1995) Stochastic programming. Kluwer Academic Publishers, Dordrecht
Shestak V, Smith J, Uml R, Hale J, Moranville P, Maciejewski AA, Siegel HJ (2006) Greedy approaches to static stochastic robust resource allocation for periodic sensor driven distributed systems. In: Proceedings of the 2006 international conference on parallel and distributed processing techniques and applications (PDPTA06), pp 3–9
Singh AK, Shafique M, Kumar A, Henkel J (2013) Mapping on multi/many-core systems: survey of current and emerging trends. In: Proceedings of the 50th annual design automation conference, DAC ’13. ACM, New York, NY, pp 1:1–1:10
Sirdey R (2011) Contributions á l’optimisation combinatoire pour l’embarqué: des autocommutateurs cellulaires aux microprocesseurs massivement paralléles. HDR, UTC, France
Srinivasan K, Chatha K (2005) A technique for low energy mapping and routing in Network-on-Chip architectures. In: ISLPED ’05, pp 387–392
Stan O, Sirdey R, Carlier J, Nace D (2012) A heuristic algorithm for stochastic partitioning of process networks. In: Proceedings of the 16th IEEE international conference on system theory, control and computing (ICSTCC), pp 1–6
Stan O, Sirdey R, Carlier J, Nace D (2013) A GRASP for placement and routing of dataflow process networks on manycore architectures. In: Eight international conference on P2P, parallel, grid, cloud and internet computing (3PGCIC)
Stone H (1977) Multiprocessor scheduling with the aid of network flow algorithms. IEEE Trans Softw Eng 3(1):85–93
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Stan, O., Sirdey, R., Carlier, J. et al. A GRASP metaheuristic for the robust mapping and routing of dataflow process networks on manycore architectures. 4OR-Q J Oper Res 13, 309–334 (2015). https://doi.org/10.1007/s10288-015-0280-0
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DOI: https://doi.org/10.1007/s10288-015-0280-0