Abstract
The usual approach in parallelizing SAT and SMT solvers is either to explore different parts of the search space in parallel (divide-and-conquer approach) or to run multiple instances of the same solver with suitably altered parameters in parallel, possibly exchanging some information during the solving process (parallel portfolio approach). Quite a different approach is to parallelize the execution of time-consuming algorithms that check for satisfiability and propagations during the search space exploration. Since most of the execution time is spent in these procedures, their efficient parallelization might be a promising research direction. In this paper we present our experience in parallelizing the simplex algorithm which is typically used in the SMT context to check the satisfiability of linear arithmetic constraints. We provide a detailed description of this approach and present experimental results that evaluate the potential of the approach compared to the parallel portfolio approach. We also consider the combination of the two approaches.
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Notes
For efficiency, most modern SMT solvers use multiprecision arithmetic only when needed, i.e. the built-in hardware arithmetic is used until an overflow is detected.
In practice, the set of possible relations is more general, that is \(\bowtie \in \{\le , \ge , <, >, =, \ne \}\). However, the symbols \(\ne \) and \(=\) can be easily eliminated in the preprocessing stage (\(x = y\) is replaced by \(x \le y \wedge x \ge y\) and \(x \ne y\) is replaced by \(x < y \vee x > y\)). The only non trivial part is the elimination of strict inequalities. This is done by considering the vector space \({\mathbb {Q}}_\delta \) of pairs of rationals instead of \({\mathbb {Q}}\). See Dutertre and Moura (2006) for details.
The bounds data structure is most efficiently implemented as a hash map that assigns a pair of bounds (lower and upper) to each unknown.
The speedup is defined as the ratio of the times consumed by the sequential and parallel executions.
Interestingly, based on the results we obtained in the experiments, tableaux in QF_RDL instances are, actually, not sparser on average than tableaux in QF_LRA instances.
The factor 10 is arbitrarily chosen, i.e. we did not measure exactly how many times the multiprecision arithmetic is slower than the hardware arithmetic. We have also tried to use values other than 10, but the conclusions were mostly the same.
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Acknowledgments
This work was partially supported by the Serbian Ministry of Science Grant 174021 and by the SNF Grant SCOPES IZ73Z0_127979/1.
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Banković, M. Parallelizing simplex within SMT solvers. Artif Intell Rev 48, 83–112 (2017). https://doi.org/10.1007/s10462-016-9495-5
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DOI: https://doi.org/10.1007/s10462-016-9495-5