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An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks

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Abstract

In this paper, we propose an optimized, search based near-optimal mapping heuristic, named as ONMAP for mapping real time embedded application workloads on 2D based on-chip interconnection network platforms. ONMAP exploits NMAP, a well-known and fast nearest neighbor heuristic algorithm by using the modular exact optimization method. The proposed hybrid algorithm minimizes the on-chip inter-processor communication energy consumption and optimizes the interconnection network performance parameters. The algorithm inherits the constructive search based heuristic nature of the NMAP algorithm, as well as the property of exact optimization for mapping embedded applications on the target communication architecture. To verify the efficiency and effectiveness of the algorithm, we have compared the proposed algorithm with NMAP and random mapping algorithm under similar simulation environments and traffic conditions. The mapping results of the exemplary real world applications such as VOPD, PIP, MPEG4, MWD, MMS and WiFi-80211arx indicate that ONMAP algorithm is more efficient than its competitors for most of the performance parameters of the on-chip network designs. The algorithm successfully optimized the energy consumption, up to 20 % and 26% in comparison to NMAP and random algorithms, respectively. Similarly, the cost is optimized up to 10% and 60% as compared to NMAP and random mapping algorithms, respectively.

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References

  1. Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput Soc 35(1):70–78

    Article  Google Scholar 

  2. Dally WJ, Towels B (2001) Route packets, not wires, on-chip interconnection networks.. In: Proceedings of the 38th DAC, Las Vegas, Nevada, USA, pp 684–689. ISBN:1-58113-297-2. https://doi.org/10.1145/378239.379048

  3. Jantch A, Tenhunen H (2003) Networks on chip. Kluwer Academic Publishers, Norwell

    Book  Google Scholar 

  4. Atienza D, Angiolini F, Murali S et al (2008) Network-on-chip design and synthesis outlook. VLSI J 41:340–359

    Article  Google Scholar 

  5. Tsai WC, Lan YC, Hu YH, et al (2012) Networks on chips: structure and design methodologies. Hindawi J Electric Comput Eng, Article ID 509465, 15 pp

  6. Marculescu R, Ogras UY, Peh LS, et al (2009) Outstanding research problems in NoC design: systems, micro architecture, and circuit perspectives. IEEE Trans Computer-Aided Des Integr Circ Syst 28(1):03–21

    Article  Google Scholar 

  7. Wu C, Deng C, Liu L et al (2017) A Multi-objective model oriented mapping approach for noc based computing systems. IEEE Transactions on Parallel Distributed Systems 28(3):662–676

    Article  Google Scholar 

  8. Khan S, Anjum S, Gulzari UA, et al (2018) Comparative analysis of Network-on-Chip simulation tools. IET Comput Digit Tech 12(1):30–38

    Article  Google Scholar 

  9. Gulzari UA, Khan S, Anjum S et al (2017) An efficient and scalable cross-bypass-mesh architecture for on-chip communication. IET Comput Digit Tech 11(4):140–148

    Article  Google Scholar 

  10. Gulzari UA, Anjum S, Torres FS et al (2016) A new cross-by-pass-torus architecture based on CBP-mesh and torus interconnection for on-chip communication. PLoS ONE 11(12):1–18,e0167590

    Article  Google Scholar 

  11. Anjum S, Jie C, PEI-PEI Y (2008) Traffic Modeling and Mapping of H.264 Encoder on 2D-Mesh Vs Application Specific NoC. Journal of System Simulation 20(10):2782–2788

    Google Scholar 

  12. Sahu S, Kittur HM (2013) Area and power efficient network-on-chip router architecture.. In: 2013 IEEE conference on information & communication technologies (ICT) India, pp 855–859, ISBN:13653575. https://doi.org/10.1109/CICT.2013.6558214

  13. Walter I, Cidon I, Kolodny A, et al (2009) The era of many-modules SoC: revisiting the NoC mapping problem. 2nd. Int. Workshop on Network on Chip Architectures, New York, NY, USA, pp 43–48. ISBN:978-1-60558-774-5. https://doi.org/10.1145/1645213.1645224

  14. Mottaghi M (2014) DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors. Elsevier journal of Microprocessors and Microsystems 38(1):88–97

    Article  Google Scholar 

  15. Kumar Sahu P, Chattopadhyay S (2013) A survey on application mapping strategies for network-on-chip design. J Syst Archit 59:60–76

    Article  Google Scholar 

  16. Tosun S, Ozturk O, Ozen M (2009) An ILP formulation for application mapping onto Network-on-Chips.. In: 2009 international conference on application of information and communication technologies, Baku, Azerbaijan, pp 1–5, INSPEC: 11051086. https://doi.org/10.1109/ICAICT.2009.5372524

  17. Tosun S (2011) New heuristic algorithm for energy aware application mapping and routing on mesh-based NoCs. Journal of System Architecture 57(1):69–78

    Article  Google Scholar 

  18. Singh AK, Srikanthan T, Kumar A, et al (2010) Communication-aware heuristics for run-time task mapping on NoC-based MPSoc platforms. J. Syst. Archit. 56(7):242–255

    Article  Google Scholar 

  19. Bhardwaj K, JENA RK (2009) Energy and bandwidth aware mapping of IPs onto regular NoC architectures using multi-objective genetic algorithms. 2009 International Symposium on System-on-Chip. Tampere, Finland, pp 27–31, INSPEC: 10976455. https://doi.org/10.1109/SOCC.2009.5335684

  20. Khan S, Anjum S, Gulzari UA et al (2017) Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture. IEEE Access PP(99):13

    Google Scholar 

  21. Shen T, Chao CH, Lien YK, Wu AY, et al (2007) A new binomial mapping and optimization algorithm for reduced-complexity Mesh-based on-chip network. First International Symposium on Networks-on-Chip (NOCS’07), Princeton, USA, pp 317–322, ISBN:0-7695-2773-6. https://doi.org/10.1109/NOCS.2007.5

  22. Xua C, Liu Y, Zhu Z et al (2017) An efficient energy and thermal-aware mapping for regular network-on-chip. IEICE Electronics Express 17(14):1–11

    Google Scholar 

  23. Lei W, Xiang L (2010) Energy- and latency-aware NoC mapping based on discrete particle swarm optimization.. In: 2010 international conference on communications and mobile computing IEEE, Shenzhen, China, pp 263–268, INSPEC: 11309976. https://doi.org/10.1109/CMC.2010.38

  24. Hu J, Marculescu R (2003) Energy-aware mapping for tile-based NoC architectures under performance constraints.. In: ASP-DAC ’03 proceedings of the 2003 Asia and South Pacific design automation conference, Kitakyushu, Japan, pp 233–239. ISBN:0-7803-7660-9. https://doi.org/10.1145/1119772.1119818

  25. Lei T, Kumar S (2003) A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. Proceedings of the Euromicro Symposium on Digital System Design IEEE, pp 180–187

  26. Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. Proc. of IEEE/ACM Design, Automation and Test in Europe Conference, Paris, France 2:896–901

    Article  Google Scholar 

  27. Lu Z, Xia L, Jantch A (2008) Cluster-based simulated annealing for mapping cores onto 2-D Mesh networks on chip. In: Proceedings of the 11th Workshop on Design and Diagnostics of Electronic Circuits and Systems. IEEE Computer Society, USA, pp 1–6

  28. Radu C, Vintan L (2011) Optimized Simulated Annealing for Network-on-Chip Application Mapping. Proceedings of the 18th International Conference on Control Systems and Computer Science, Romania, pp 452–459

  29. Ascia G, Catania V (2004) Multi-Objective Mapping for Mesh Based NoC Architectures. Proceedings of the ICHSC/ICSS, Stockholm, Sweden, pp 182–187

  30. Jena RK (2012) Application mapping of Mesh based NoC using Evolutionary algorithm. J Inf Syst Commun 3(1):203–206

    MathSciNet  Google Scholar 

  31. Sepulveda MJ, Strum M, Chau WJ, et al (2011) A Multi-Objective Approach for Multi-Application NoC Mapping. IEEE Latin American Symposium on Circuits and Systems (LASCAS), Bogata, Colombia, pp 1–4, INSPEC: 11945802. https://doi.org/10.1109/LASCAS.2011.5750275

  32. Harmanani HM (2008) A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area.. In: 2008 joint IEEE North-East workshop on circuits and systems and TAISA conference, NEWCAS-TAISA. pp 29–32. https://doi.org/10.1109/NEWCAS.2008.4606313

  33. Tran AT, Baas BM (2012) NoCT weak: a highly parameterizable simulator for early exploration of performance and energy of networks on chip. Technical Report, VLSI Computation Lab, ECE Department, UC Davis

  34. Hassan AS, Morgan AA, El-Kharashi MW (2016) ’An Enhanced Network-on-Chip Simulation for Cluster-Based Routing’. The 3rd International Workshop on Design and Performance of Networks on Chip (DPNoC) 94:410–417

    Google Scholar 

  35. Koziris N, Romesis M, Tsanakas P, Papakonstantinou G (2000) An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures. Proceedings of the 8th Euro PDP, pp 406–413

  36. Hu J, Marculescu M (2005) Energy and performance aware mapping for regular NoC architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(4):551–562

    Article  Google Scholar 

  37. Srinivasan K, Chatha KS (2005) A technique for low energy mapping and routing in Network-on-Chip architecture. In: Proceedings of the 2005 international symposium on low power electronics and design ISLPED ’05, San Diego, CA, USA, 387-392, ISBN:1-59593-137-6. https://doi.org/10.1145/1077603.1077695

  38. Chen Y, Xie L, Li J (2009) An energy-aware heuristic constructive mapping algorithm for network on chip. In: IEEE 8th international conference on ASIC (ASICON), Hunan, China, pp 101–104, INSPEC: 11009365. https://doi.org/10.1109/ASICON.2009.5351596

  39. Jang W, Pan DZ (2010) A3MAP: Architecture-aware analytic mapping for Network-on-Chip.. In: 15th Asia and South Pacific design automation conference (ASP-DAC), Taipei, Taiwan, pp 523–528, INSPEC: 11153807. https://doi.org/10.1109/ASPDAC.2010.5419827

  40. Reshadi M, Khademzadeh A, Reza A (2010) Elixir: a new bandwidth-constrained mapping for Networks-on-Chip. IEICE Electronics Express 7(2):73–79

    Article  Google Scholar 

  41. Tavanpour M, Khademzadeh A, Janidarmian M (2009) Chain-mapping for mesh based Network-on-Chip architecture. IEICE Electronics Express 6(22):1535–1541

    Article  Google Scholar 

  42. Fen G, Ning W (2010) Genetic algorithm based mapping and routing approach for network on chip architectures. Chin J Electron 19(1):91–96

    Google Scholar 

  43. Tosun S, Ozturk O, Ozkan E, Ozen M (2015) Application mapping algorithms for mesh-based network-on-chip architectures. Journal of Supercomputers 71:995–1017

    Article  Google Scholar 

  44. Alikhah-Asl E, Reshadi M (2017) XY-Axix and Distance Based NoC Mapping, 8th international symposium on telecommunication (IST), Tehran, pp 1–6

  45. Xua C, Liu Y, Zhu Z, Yang Y (2017) An efficient energy and thermal-aware mapping for regular network-on-chip. IEICE Electronics Express 14(17):1–11

    Google Scholar 

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Acknowledgements

The present research has been conducted by the Research Grant of Kwangwoon University in 2018.

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Authors and Affiliations

  1. Department of Electrical Engineering, Comsats Institute of Information Technology, Wah, 47040, Pakistan

    Sarzamin Khan

  2. Department of Computer Science, Comsats Institute of Information Technology, Wah, 47040, Pakistan

    Sheraz Anjum & Muhammad Khalil Afzal

  3. Department of Electrical Engineering, The University of Lahore, Islamabad, Pakistan

    Usman Ali Gulzari

  4. Department of Electronics and Communication Engineering, Kwangwoon University, Seoul, South Korea

    Farruh Ishmanov

  5. University of Catania, V.le A. Doria 6, Catania, 95125, Italy

    Maurizio Palesi

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  1. Sarzamin Khan
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  2. Sheraz Anjum
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Correspondence to Farruh Ishmanov.

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Khan, S., Anjum, S., Gulzari, U.A. et al. An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks. Appl Intell 48, 4792–4804 (2018). https://doi.org/10.1007/s10489-018-1246-7

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