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An efficient lightweight CNN acceleration architecture for edge computing based-on FPGA

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Abstract

With the system performance, volume and power restriction requirements in edge computing, single chip based on Field Programmable Gate Array (FPGA), with the characteristics of parallel execution, flexible configuration and power efficiency, is more desirable for realizing Convolutional Neural Network (CNN) acceleration. However, implementing a lightweight CNN with limited on-chip resources while maintaining high computing efficiency and utilization is still a challenging task. To achieve efficient acceleration with single chip, we implement Network-on-Chip (NoC) based on Processing Element (PE) that consists of multiple node arrays. Moreover, the computing and memory efficiencies of PE are optimized with a sharing function and hybrid memory. To maximize resource utilization, a theoretical model is constructed to explore the parallel parameters and running cycles of each PE. In the experimental results of LeNet and MobileNet, resource utilization values of 83.61% and 95.28% are achieved, where the throughput values are 53.3 Giga Operations Per Second (GOPS) and 41.9 GOPS, respectively. Power measurements show that the power efficiency is optimized to 77.25 GOPS/W and 85.51 GOPS/W on our platform, which is sufficient to realize efficient inference for edge computing.

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Acknowledgements

This work was supported in part by the National Natural Science Foundation of China(NSFC) under Grant 62171156.

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Authors and Affiliations

  1. School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, 150001, China

    Ruidong Wu, Bing Liu, Ping Fu & Haolin Chen

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  1. Ruidong Wu
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  2. Bing Liu
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Correspondence to Bing Liu.

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Wu, R., Liu, B., Fu, P. et al. An efficient lightweight CNN acceleration architecture for edge computing based-on FPGA. Appl Intell 53, 13867–13881 (2023). https://doi.org/10.1007/s10489-022-04251-3

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