Abstract
Several researches have been done in literature to improve the resolution of pulse mode architectures used for controlling the DC–DC converters. Resolution can be measured as the number of bits used for representing the duty cycle control input [1]. Higher the resolution of control inputs more precisely the changes in output voltage with DC–DC converter can be addressed [2]. Traditional architectures implemented with counter and other delay line structure occupies large area and also has less throughput with an increase in number of control inputs. But the DC–DC converters used in portable and mobile based applications must be compact and consumes low power [3]. This proposed DPWM architecture uses Block RAM available in FPGA to store the binary bit patterns to derive variable duty cycle pulses [4]. The architecture is proposed for three different control inputs like four bit, three bit and two bit control inputs. This proposed architecture for a four bit control input can address 4096 bit patterns and has maximum operating clock frequency of 306.84 megahertz (MHz).
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Radhika, V., Baskaran, K. High resolution DPWM clustered architecture for digitally controlled DC–DC converter using FPGA. Cluster Comput 22 (Suppl 2), 4421–4430 (2019). https://doi.org/10.1007/s10586-018-1990-9
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DOI: https://doi.org/10.1007/s10586-018-1990-9