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Platform designer: An approach for modeling multiprocessor platforms based on SystemC

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Abstract

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.

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Authors and Affiliations

  1. Informatics Center (CIn), Federal University of Pernambuco, Cidade Universitaria 50740-540, Recife, PE, Brazil

    Cristiano Araujo, Millena Gomes & Edna Barros

  2. Institute of Computing, University of Campinas, Cidade Universitaria Zeferino Vaz, PO. Box 6176, Campinas-SP, Brazil

    Sandro Rigo, Rodolfo Azevedo & Guido Araujo

Authors
  1. Cristiano Araujo
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  2. Millena Gomes
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  3. Edna Barros
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  4. Sandro Rigo
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  5. Rodolfo Azevedo
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  6. Guido Araujo
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Araujo, C., Gomes, M., Barros, E. et al. Platform designer: An approach for modeling multiprocessor platforms based on SystemC. Des Autom Embed Syst 10, 253–283 (2005). https://doi.org/10.1007/s10617-006-0654-9

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  • DOI: https://doi.org/10.1007/s10617-006-0654-9

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