Abstract
The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.
Similar content being viewed by others
References
Bergeron, J. Functional Verification of HDL Models, 2nd edition. Kluwer Academic Publisher, Boston, 2003.
Brahme, D.S., S. Cox, J. Gallo, W. Grundmann, C.N. Ip, W. Paulsen, J.L. Pierce, J. Rose, D. Shea, and K. Whiting. The Transaction-Based Verification Methodology. Technical Report CDNL-TR-2000-0825, Cadence Berkeley Labs, 2000.
BrazilIp.www.brazilip.org.br/fenix, 2005.
Collins-Sussman, B., B.W. Fitzpatrick, and C.M. Pilato. Version control with subversion, 2004.
da Silva, K.R.G., E.U.K. Melcher, G. Araujo, and V.A. Pimenta. An Automatic Testbench Generation Tool for a Systemc Functional Verification Methodology. In SBCCI ’04: Proceedings of the 17th Symposium on Integrated Circuits and System Design, ACM Press, New York, NY, USA, pp. 66–70, 2004.
Dueñas, C.A. Verification and Test Challenges in soc Designs. Invited Talk, 2004.
Piziali, A. Functional Verification Coverage Measurement and Analysis 1st edition. Kluwer Academic Publisher, Massachusetts, USA, 2004.
Randjic, A., N. Ostapcuk, I. Soldo, P. Markovic, and V. Mujkovic. Complex Asics Verification with Systemc. In 23rd International Conference on Microelectronics, pp. 671–674, 2002.
Swan, S. An Introduction to System Level Modelling in Systemc 2.0, 2001.
Team, X. Xvid api 2.1 reference (for 0.9.x series), 2003.
Wagner, I., V. Bertacco, and T. Austin. Stresstest: An Automatic Approach to Test Generation via Activity Monitors. In Design Automation Conference, 2005.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Silva, K.R.G.d., Melcher, E.U.K., Maia, I. et al. A methodology aimed at better integration of functional verification and RTL design. Des Autom Embed Syst 10, 285–298 (2005). https://doi.org/10.1007/s10617-006-9587-6
Issue Date:
DOI: https://doi.org/10.1007/s10617-006-9587-6