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ASDeX: a formal specification for analog circuit enabling a full automated design validation

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Abstract

In this paper an XML based language format to describe specifications of analog IPs and its usage in a validation flow is presented. With the help of an XML-Schema-Definition (XSD) a specification description language called Analog Specification Description in XML (ASDeX) is introduced. An ASDeX-file contains not only specification parameters but also measurement definitions and testbenches to enable specification validation based on simulation. The intention is to generate executable modules (tasks) for running simulations and extracting and checking the actual property values of analog circuits. The task generation is based on a generic template approach using a Meta-Simulator to achieve vendor independent analog IP representation including IP verification.

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Notes

  1. LVDS: low-voltage differential signaling.

  2. The Essence Framework was a part work of the VISION project (funding label: 01 M 3078). This project is partly supported in accordance with the BMBF “Nanoelectronics” sponsorship scheme within the scope of the Ekompass-sponsorship complex of the Federal Ministry of Education and Research (BMBF).

  3. The Meta-Simulator is a PERL software library and developed by Infineon Technologies AG, Germany.

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Authors and Affiliations

  1. Department of Computer Science, Goethe University of Frankfurt am Main, Robert-Mayer-Str. 11-15, 60325, Frankfurt am Main, Germany

    Mingyu Ma & Lars Hedrich

  2. IFX DES IP LIB, Infineon Technologies AG, Am Campeon 1-12, 85579, Neubiberg, Germany

    Christian Sporrer

Authors
  1. Mingyu Ma
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  2. Lars Hedrich
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  3. Christian Sporrer
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Corresponding author

Correspondence to Mingyu Ma.

Additional information

This work was partly developed within the project SyEnA (project label 01 M 30 86) which is funded within the Research Program ICT 2020 by the German Federal Ministry of Education and Research (BMBF).

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Ma, M., Hedrich, L. & Sporrer, C. ASDeX: a formal specification for analog circuit enabling a full automated design validation. Des Autom Embed Syst 18, 99–118 (2014). https://doi.org/10.1007/s10617-012-9088-8

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  • DOI: https://doi.org/10.1007/s10617-012-9088-8

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