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Fault buffers

Enabling near-true voltage scaling in variation-sensitive L1 caches

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Abstract

Voltage scaling can be applied to cache memories to reduce their energy consumptions. However, reduced supply voltage to the cache memories increases the number of defective SRAM cells due to process variations, which will decrease their yields and nullify the benefits of voltage scaling. To mitigate this problem, we propose a fault buffer-based scheme for L1 caches. Faults are identified and isolated at the granularity of individual words in the L1 caches. Actively used faulty cache words are dynamically allocated in the fault buffers. The fault buffers are organized as multiple banks for low cost implementation and can be dynamically reconfigured to reflect varying performance demands of programs. This dynamic scheme is shown to be more energy- and area-efficient than, and to be performing comparably to, the previously proposed static schemes.

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Notes

  1. The word “Word” should be interpreted in the context of the cited reference.

  2. Content-addressable-memory.

  3. For example, eight Defect-mark bits increase the path effort by 38 % (assuming tagline=19tag+1v+1lru) but effort delay is within 5 % for N greater than 6 (D e =N×F −N).

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Acknowledgements

This research was supported by the National Research Foundation of Korea (NRF) grants funded by the Ministry of Education, Science and Technology (2011-0005378, 2012-0000980) and by the Ministry of Knowledge and Economics (10041313).

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Authors and Affiliations

  1. Department of Information & Communication Engineering, Korea Advanced Institute of Science & Technology, Daejeon, South Korea

    Tayyeb Mahmood

  2. Department of Computer Science, Korea Advanced Institute of Science & Technology, Daejeon, South Korea

    Soontae Kim

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  1. Tayyeb Mahmood
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  2. Soontae Kim
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Correspondence to Tayyeb Mahmood.

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Mahmood, T., Kim, S. Fault buffers. Des Autom Embed Syst 17, 411–438 (2013). https://doi.org/10.1007/s10617-012-9104-z

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