Skip to main content

Advertisement

SpringerLink
Log in

Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

Multiprocessor System-on-Chip (MPSoC) systems are evolving towards a processor pool-based architecture that employs hierarchical on-chip networks for inter- and intra-processor pool communication. Since the design space of processor pool-based MPSoCs is extremely wide, the application-specific optimization of on-chip communication architecture is a nontrivial task. This paper presents a systematic methodology for a cascaded bus matrix-based on-chip network design for processor pool-based MPSoCs. Our approach finds sub-optimal architectures in terms of energy consumption and on-chip area while satisfying given performance constraints. The proposed approach allows for independent configurations of processor pools, which leads to better solutions than seen in previous work. Since a simulation is too time-consuming to evaluate the performance of complex on-chip networks, we propose to prune the designs space efficiently by two static analysis techniques to minimize the use of simulations. Thanks to the static analysis techniques, our approach achieves an order of magnitude speed improvement for architecture exploration without performance loss, compared with simulation-based approaches.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

Notes

  1. \(\mathbb{N}_{+}\) and \(\mathbb{R}_{+}\) mean positive natural numbers and positive real numbers respectively.

  2. This example is borrowed from [7].

References

  1. AXI (2004) ARM. http://www.arm.com/products/solutions/AMBA3AXI.html

  2. Bertozzi D, Jalabert A, Murali S, Tamhankar R, Stergiou S, Benini L, De Micheli G (2005) NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans Parallel Distrib Syst 16(2):113–129

    Article  Google Scholar 

  3. Brooks D, Tiwari V, Martonosi M (2000) Wattch: a framework for architectural-level power analysis and optimizations. In: Proc international symposium on computer architecture, Jun 2000, pp 83–94

    Google Scholar 

  4. Chandrakasan AP, Brodersen RW (1995) Minimizing power consumption in digital CMOS circuits. Proc IEEE 83(4):498–523

    Article  Google Scholar 

  5. Chou C-L, Marculescu R (2010) Designing heterogeneous embedded network-on-chip platforms with users in mind. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(9):1301–1314

    Article  Google Scholar 

  6. Cong J, Huang Y, Yuan B (2011) ATree-based topology synthesis for on-chip network. In: Proc international conference on computer-aided design, Nov 2011, pp 651–658

    Google Scholar 

  7. Han K-H, Kim J-H (2002) Quantum-inspired evolutionary algorithm for a class of combinatorial optimization. IEEE Trans Evol Comput 6(6):580–593

    Article  Google Scholar 

  8. Hur JY, Wong S, Stefanov T (2010) Design trade-offs in customized on-chip crossbar schedulers. J Signal Process Syst 58(1):69–85

    Article  Google Scholar 

  9. CACTI (2008) HP. http://www.hpl.hp.com/research/cacti

  10. Hu J, Ogras UY, Marculescu R (2006) System-level buffer allocation for application-specific networks-on-chip router design. IEEE Trans Comput-Aided Des 25(12):2919–2933

    Article  Google Scholar 

  11. Jang Y, Kim J, Kyung C-M (2010) Topology synthesis for low power cascaded crossbar switches. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(12):2041–2045

    Article  Google Scholar 

  12. Joo Y-P, Kim S, Ha S (2009) On-chip communication architecture exploration for processor-pool-based MPSoC. In: Proc design automation and test in Europe, Apr 2009, pp 466–471

    Google Scholar 

  13. Joo Y-P, Kim S, Ha S (2011) Fast communication architecture exploration for processor pool-based MPSoC via static performance analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(3):468–472

    Article  Google Scholar 

  14. Jun M, Yoo S, Chung E-Y (2008) Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. In: Proc Asia South Pacific design automation conference, Jan 2008, pp 583–588

    Google Scholar 

  15. Kim H, Yun D, Ha S (2009) Scalable and retargetable simulation techniques for multiprocessor systems. In: Proc international conference on hardware/software codesign and system synthesis, Oct 2009, pp 89–98

    Google Scholar 

  16. Kim S, Ha S (2006) Efficient exploration of bus-based system-on-chip architectures. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(7):681–692

    Article  Google Scholar 

  17. Kim S, Im C, Ha S (2005) Schedule-aware performance estimation of communication architecture for efficient design space exploration. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(5):539–552

    Article  Google Scholar 

  18. Lahiri K, Raghunathan A, Dey S (2004) Design space exploration for optimizing on-chip communication architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 23(6):952–961

    Article  Google Scholar 

  19. Lahiri K, Raghunathan A, Dey S (2001) Evaluation of the traffic-performance characteristics of system-on-chip communication architectures. In: Proc VLSI design, Jan 2001, pp 21–35

    Google Scholar 

  20. Mahgoub IO, Elmagarmid AK (1992) Performance analysis of a generalized class of m-level hierarchical multiprocessor systems. IEEE Trans Parallel Distrib Syst 3(2):129–138

    Article  Google Scholar 

  21. McGhan H (2006) Niagara 2 opens the floodgates. Microprocessor Rep, Nov 2006

  22. Mudge TN, Makrucki BA (1982) Probabilistic analysis of a crossbar switch. ACM SIGARCH Comput Archit News 10(3):311–320

    Article  Google Scholar 

  23. Murali S, Benini L, De Micheli G (2007) An application-specific design methodology for on-chip crossbar generation. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(7):1283–1296

    Article  Google Scholar 

  24. Murali S, Seiculescu C, Benini L, De Micheli G (2009) Synthesis of networks on chips for 3D systems on chips. In: Proc Asia South Pacific design automation conference, Jan 2009, pp 242–247

    Google Scholar 

  25. Ogras UY, Marculescu R (2010) An analytical approach for network-on-chip performance analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(12):2001–2013

    Article  Google Scholar 

  26. Paolucci PS, Jerraya AA, Leupers R, Thiele L, Vicini P (2006) SHAPES: a tiled scalable software hardware architecture platform for embedded systems. In: Proc international conference on hardware/software codesign and system synthesis, Oct 2006, pp 167–172

    Chapter  Google Scholar 

  27. Pasricha S, Dutt ND, Bozorgzadeh E, Ben-Romdhane M (2006) FABSYN: floorplan-aware bus architecture synthesis. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(3):241–253

    Article  Google Scholar 

  28. Pasricha S, Dutt ND, Ben-Romdhane M (2007) BMSYN: bus matrix communication architecture synthesis for MPSoC. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(8):1454–1464

    Article  Google Scholar 

  29. Radulescu A, Dielissen J, Pestana SG, Gangwal OP, Rijpkema E, Wielage P, Goossens K (2005) An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans Comput-Aided Des Integr Circuits Syst 24(1):4–17

    Article  Google Scholar 

  30. Ryu KK, Mooney VJ III (2004) Automated bus generation for multiprocessor SoC design. IEEE Trans Comput-Aided Des 23(11):1531–1549

    Article  Google Scholar 

  31. STBus Interconnect (2003) STMicroelectronics. http://www.st.com/stonline/products/technologies/soc/stbus.htm

  32. Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Iyer P, Singh A, Jacob T, Jain S, Venkataraman S, Hoskote Y, Borkar N (2007) An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS. In: Digest technical papers of IEEE international solid-state circuits conference, Feb 2007, pp 98–589

    Google Scholar 

  33. Weber W-D, Chou J, Swarbrick I, Wingard D (2005) A quality-of-service mechanism for interconnection networks in system-on-chips. In: Proc design, automation and test in Europe, Mar 2005, pp 1232–1237

    Chapter  Google Scholar 

  34. Yoo J, Yoo S, Choi K (2009) Topology/floorplan/pipeline co-design of cascaded crossbar bus. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(8):1034–1047

    Article  Google Scholar 

Download references

Acknowledgements

This research was supported by Center for Advanced Image and Information Technology, Chonbuk National University, and research funds of Chonbuk National University in 2011, and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0023325). This research was partly supported by the MKE (The Ministry of Knowledge Economy), Korea, under the ITRC (Information Technology Research Center) support program supervised by the NIPA (National IT Industry Promotion Agency) (NIPA-2013-H0301-13-1011).

Author information

Authors and Affiliations

  1. Samsung Electronics, Gyeonggi, 446-711, Korea

    Young-Pyo Joo

  2. Division of Computer Science and Engineering, Chonbuk National University, Jeonju, Jeonbuk, 561-756, Korea

    Sungchan Kim

  3. School of Computer Science and Engineering, Seoul National University, Seoul, 151-744, Korea

    Soonhoi Ha

Authors
  1. Young-Pyo Joo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sungchan Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Soonhoi Ha
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sungchan Kim.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Joo, YP., Kim, S. & Ha, S. Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC. Des Autom Embed Syst 16, 293–317 (2012). https://doi.org/10.1007/s10617-013-9110-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10617-013-9110-9

Keywords

Search

Navigation