Abstract
A hybrid solid-state drive (SSD) consisting of both single-level-cell (SLC) and multi-level-cell (MLC) flash chips achieves a response time as fast as an SLC-flash-based SSD while maintaining the price of an MLC-flash-based SSD. It is supported by a software layer called flash translation layer (FTL) that contains an algorithm to efficiently store hot and cold data in the SLC- and MLC-flash chips, respectively. Unfortunately, previous FTLs for hybrid SSDs depended hot data identification solely on the write commands’ request size and reused former address mapping algorithms for managing the SLC- and MLC-flash chips. To address this limitation, we propose a “data pattern aware FTL (DPA-FTL)” algorithm. DPA-FTL enhances the hot data identification process by considering two characteristics of hot data: frequent update and irregular allocation. Furthermore, it compares former address mapping algorithms and selects a more appropriate algorithm for the hybrid SSD. According to our performance evaluation, DPA-FTL reduces the overall number of write and erase operations and reduces the deviation of erase operations.
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Notes
Program/erase cycle limit: the maximum number of writes/erases allowed for each block.
Hot data: frequently updated data
Partial programming: byte-unit-write operation which allows to re-access a page without an erase operation.
Logical page number: fixed logical group of logical sectors.
Random data in/out: a technique which allows to write/modify (random data in) or read (random data out) in the unit of byte.
Merge operation: a process of reclaiming a data block.
Log-block pool: a list which contains the physical addresses of unallocated log-blocks.
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Kwon, S.J., Chung, TS. Data pattern aware FTL for SLC+MLC hybrid SSD. Des Autom Embed Syst 19, 101–127 (2015). https://doi.org/10.1007/s10617-014-9138-5
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DOI: https://doi.org/10.1007/s10617-014-9138-5