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Cluster based MPSoC architecture: an on-chip message passing implementation

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Abstract

This paper proposes a hardware memory management unit to implement an on-chip message passing protocol for cluster based multi-processors system on chip architectures. Within the architecture each cluster is composed of general purpose processors or digital signal processors, along with a memory. To maintain the coherence of the memory a hardware memory management unit is added in the cluster to increase the performance and support an on-chip message passing communication. The hardware memory management unit has the capacity to allocate, control and limit the access to the memory. In order to show the benefit of our architecture a performance comparison over a classical flat architecture and against a state of the art architecture is driven. The results show an improvement that ranges from 1.2 to 21.77 % over these two architectural models. Finally the hardware cost overhead is studied.

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Acknowledgments

This research is sponsored by the European Commission under the 7th Framework program within the FlexTiles project (FP7 ICT-288248).

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Authors and Affiliations

  1. IETR, LUNAM University, University of Nantes, Rue Christian Pauc, 44306, Nantes, France

    Romain Brillu & Sébastien Pillement

  2. Thales Research & Technology, 1 Avenue Augustin Fresnel, 91767, Palaiseau, France

    Romain Brillu, Fabrice Lemonnier & Philippe Millet

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  1. Romain Brillu
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  2. Sébastien Pillement
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  3. Fabrice Lemonnier
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  4. Philippe Millet
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Correspondence to Romain Brillu.

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Brillu, R., Pillement, S., Lemonnier, F. et al. Cluster based MPSoC architecture: an on-chip message passing implementation. Des Autom Embed Syst 17, 587–607 (2013). https://doi.org/10.1007/s10617-014-9146-5

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  • DOI: https://doi.org/10.1007/s10617-014-9146-5

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