Abstract
Rising data rates and input/output density in integrated circuits are challenging the traditional off-chip copper interconnect solutions, demanding a compatible high-speed serial interface capable of maintaining multi-gigabits data rates. Designers typically choose copper interconnect for chip-to-chip connections in a Multi-FPGA System (MFS). However, copper based interconnects are incapable of scaling up with the data rate and exhibit lossy characteristics with increasing frequency. Performance of an MFS can be enhanced if the off-chip electrical interconnects are replaced by short-range optical interconnects. Additionally, the selection of MFS inter-chip communication strategy also affects system performance. We have proposed latency-optimized MFS with serial optical interface with two different inter-chip communication strategies. The proposed architectures were experimentally evaluated using six real world benchmark circuits and provided an average system frequency gain of nearly 22%, compared to conventional MFS.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Edin K (2011) An FPGA implementation for a high-speed optical link with aPCIe interface. Ph. D Thesis, McGill University
Kuzmin A, Fey D, Lohmann U (2014) An integrated into FPGA system for optical link testing and parameters tuning. Int J Adv Syst Measure 7(1&2):141–149
Li MP (2011) Overcome copper limits with optical interfaces. Altera White Paper
Li MP, Martinez J, Vaughan D (2012) Transferring high-speed data over long distances with combined FPGA and multichannel optical modules. Altera White Papers, pp 1–6
Gilpatric M (2012) Pluggable optical interfaces and their compatibility with Xilinx FPGAs’, Xilinx White Paper
Deng B, Liu C, Chen J et al (2015) JTAG-based remote configuration of FPGAs over optical fibers. J Instrum 10(01):C01050
Minami S, Hoffmann J, Kurz N et al (2011) Design and implementation of a data transfer protocol via optical fiber. IEEE Trans Nucl Sci 58(4):1816–1819
‘UltraScale Architecture GTY Transceivers, User Guide’, December 2016. http://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf. Accessed 23 Apr 2017
Booth B, Bottoms B, Buther S et al (2013) On-Board Optical Interconnection, CTR III TWG Report #3. MIT Microphotonics Center
Liu S, Cheng Q, Madarbux MR et al (2015) Low latency optical switch for high performance computing with minimized processor energy load. J Opt Commun Netw 7(3):A498–A510
Kim J, Choi K, Loh G (2012) Exploiting new interconnect technologies in on-chip communication. IEEE J Emerg Sel Top Circuits Syst 2(2):124–136
Datta I, Datta D, Pande PP (2014) Design methodology for optical interconnect topologies in NoCs with BER and transmit power constraints. J Lightwave Technol 32(1):163–175
Vanwassenhove L, Bockstaele R, Baets R et al. (2001) Demonstration of 2-D plastic optical fiber based optical interconnect between CMOS ICs. In: Optical fiber communication conference and exhibit, vol. 3, pp. WDD74-WDD74
‘FireFly™ Application Design Guide’, Samtec Brochure, January 2017. http://suddendocs.samtec.com/ebrochures/firefly-brochure.pdf. Accessed May 2017
‘Finisar 10G/1G dual rate (10GBASE-SR and 1000BASE-SX) 400 m Multimode Datacom SFP+Optical Transceiver Product Specification’, October 2016. https://www.finisar.com/sites/default/files/downloads/finisar_ftlx8574d3bcv_1g-10g_850nm_multimode_datacom_sfp_transceiver_productspecrevb1.pdf. Accessed 17 May 2017
Amos D, Lesea A, Richter R (2011) FPGA-based prototyping methodology manual, Synopsys
Sequeira F, Duarte D, Bilro L et al (2016) Refractive index sensing with D-shaped plastic optical fibers for chemical and biochemical applications. Sensors 16(12):2119
‘Quick look under the hood of ABC a programmer’s manual’, Berkeley Verification and Synthesis Research Centre, 2006
Sanders P, Schulz C (2013) KaHIP v0. 7–karlsruhe high quality partitioning–user guide. arXivpreprint arXiv:1311.1714
Kuznar R, Brglez F, Kozminski KA (1993) Partitioning digital circuits for implementation on multiple FPGA ICs’, MCNC Technical Report, Issue 3, Center for Microelectronics
Hitchcock RB, Smith GL, Cheng DD (1982) Timing analysis of computer hardware. IBM J Res Dev 26(1):100–105
KintexUltraScale + FPGAs Data Sheet (2016) DC and AC switching characteristics. http://www.xilinx.com/support/documentation/data_sheets/ds922-kintex-ultrascale-plus.pdf. Accessed 4 Apr 2017
Xilinx Community Forums, https://forums.xilinx.com/t5/Timing-Analysis/bd-p/TIMEANB. Accessed 19 June 2016
Xilinx Technical Support, private communication
Christoph A (2005) IWLS 2005 benchmarks. Cadence Berkeley Labs, Berkeley
Luu J, Goeders J, Wainberg M et al (2014) VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Trans Reconfigurable Technol Syst (TRETS) 7(2):1–30
Kashif A (2017) Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures. Electronic Theses and Dissertations. 7269. https://scholar.uwindsor.ca/etd/7269. Accessed 1 Aug 2017
Author information
Authors and Affiliations
Corresponding authors
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Kashif, A., Khalid, M.A.S. Experimental evaluation and comparison of latency-optimized opticaland conventional multi-FPGA systems. Des Autom Embed Syst 24, 63–77 (2020). https://doi.org/10.1007/s10617-020-09233-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10617-020-09233-7