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CAD synthesis tools for floating-gate SoC FPAAs

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Abstract

We present a tool framework to compile and program mixed-signal circuits and systems on Floating-Gate (FG) based mixed-signal System-on-Chips (SoC) consisting of a digital processor and Field Programmable Analog Array (FPAA) fabric. We have modified the configuration of Verilog-to-Routing (VTR) to cover analog circuits and developed a tool called vpr2swcs to create the list of FG switches, that is going from a high level block description of the system to the addresses and bias values on the SoC. This tool enables users to generate macro blocks and customize block location while designing mixed-signal systems on the FPAA and also enables using routing fabric, composed of FGs, for Vector Matrix Multiplication (VMM), a computing element for an analog neural network. The paper demonstrates system level examples using this tool flow, where the experimental results have been proved in other publications.

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Notes

  1. http://users.ece.gatech.edu/phasler/FPAAtool/index.html.

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Acknowledgements

The authors would like to thank Suma George for her help while debugging the tools at the early stage of development and Sung Kyu Lim for valuable comments and advice on the tools.

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Authors and Affiliations

  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA

    Sihwan Kim, Sahil Shah, Richard Wunderlich & Jennifer Hasler

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  1. Sihwan Kim
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  2. Sahil Shah
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  4. Jennifer Hasler
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Correspondence to Jennifer Hasler.

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Kim, S., Shah, S., Wunderlich, R. et al. CAD synthesis tools for floating-gate SoC FPAAs. Des Autom Embed Syst 25, 161–176 (2021). https://doi.org/10.1007/s10617-021-09247-9

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