Abstract
Hardware/software (HW/SW) partitioning is the crucial step in HW/SW co-design, which can significantly reduce the time-to-market and improves the performance of an embedded system. Due to that the majority of previous works have large exploration time and generate often low-quality solutions for large scale systems, we propose a fast HW/SW partitioning approach based on graph convolution network (GCN) to address this problem. To the best of our knowledge, it is a new partitioning method based on GCN which is a gradient-based optimization approach. It can aggressively speed up the partitioning process. To quantify the quality of solutions, the scheduling is integrated into the partitioning process. The experiment results show that not only does our proposed method outperform existing metaheuristics approaches in terms of the efficiency (e.g., 18\(\times \) faster than Kernighan–Lin algorithm for the task graphs with 1000 nodes), but it also improves the quality of HW/SW partitioning (e.g., more than 10% acceleration ratio (AR) improvement for the 1000 nodes graphs).
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Acknowledgements
The authors would like to thank my supervisors, Prof. Zebo Peng and Prof. Petru Eles, for their good ideas, valuable guidance, and patient support throughout this research. This work is supported in part by the Science and Technology Planning Project of Guangdong Province of China under Grant 2019B010140002.
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Zheng, X., Liang, S. & Xiong, X. A hardware/software partitioning method based on graph convolution network. Des Autom Embed Syst 25, 325–351 (2021). https://doi.org/10.1007/s10617-021-09255-9
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DOI: https://doi.org/10.1007/s10617-021-09255-9