Skip to main content
Log in

Event clock message passing automata: a logical characterization and an emptiness checking algorithm

  • Published:
Formal Methods in System Design Aims and scope Submit manuscript

Abstract

We are interested in modeling behaviors and verifying properties of systems in which time and concurrency play a crucial role. We introduce a model of distributed automata which are equipped with event clocks as in Alur et al. (Theor Comput Sci 211:253–273, 1999), which we call Event Clock Message Passing Automata (ECMPA). To describe the behaviors of such systems we use timed partial orders (modeled as message sequence charts with timing).

Our first goal is to extend the classical Büchi-Elgot-Trakhtenbrot equivalence to the timed and distributed setting, by showing an equivalence between ECMPA and a timed extension of monadic second-order (MSO) logic. We obtain such a constructive equivalence in two different ways: (1) by restricting the semantics by bounding the set of timed partial orders; (2) by restricting the timed MSO logic to its existential fragment. We next consider the emptiness problem for ECMPA, which asks if a given ECMPA has some valid timed execution. In general this problem is undecidable and we show that by considering only bounded timed executions, we can obtain decidability. We do this by constructing a timed automaton which accepts all bounded timed executions of the ECMPA and checking emptiness of this timed automaton.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. Akshay S, Bollig B, Gastin P (2007) Automata and logics for timed message sequence charts. In: FSTTCS. LNCS, vol 4855. Springer, Berlin, pp 290–302

    Google Scholar 

  2. Alur R, Dill DL (1994) A theory of timed automata. Theor Comput Sci 126(2):183–235

    Article  MathSciNet  MATH  Google Scholar 

  3. Alur R, Fix L, Henzinger TA (1999) Event-clock automata: A determinizable class of timed automata. Theor Comput Sci 211(1–2):253–273

    Article  MathSciNet  MATH  Google Scholar 

  4. Alur R, Holzmann G, Peled D (1996) An analyser for message sequence charts. In: TACAS. LNCS, vol 1055. Springer, Berlin, pp 35–48

    Google Scholar 

  5. Ben-Abdallah H, Leue S (1997) Timing constraints in message sequence chart specifications. In: FORTE. IFIP Conf Proc, vol 107, pp 91–106

    Google Scholar 

  6. Berthomieu B, Diaz M (1991) Modeling and verification of time dependent systems using time Petri nets. IEEE Trans Softw Eng 17(3):259–273

    Article  MathSciNet  Google Scholar 

  7. Bollig B, Leucker M (2006) Message-passing automata are expressively equivalent to EMSO logic. Theor Comput Sci 358(2–3):150–172

    Article  MathSciNet  MATH  Google Scholar 

  8. Bouyer P, Haddad S, Reynier P-A (2006) Timed unfoldings for networks of timed automata. In: ATVA. LNCS, vol 4218. Springer, Berlin, pp 292–306

    Google Scholar 

  9. Brand D, Zafiropulo P (1983) On communicating finite-state machines. J ACM 30(2):323–342

    Article  MathSciNet  MATH  Google Scholar 

  10. Büchi J (1960) Weak second order logic and finite automata. Math Log Q 5:66–92

    Google Scholar 

  11. Chandrasekaran P, Mukund M (2006) Matching scenarios with timing constraints. In: FORMATS. LNCS, vol 4202. Springer, Berlin, pp 91–106

    Google Scholar 

  12. Chatain Th, Jard C (2005) Time supervision of concurrent systems using symbolic unfoldings of time Petri nets. In: FORMATS. LNCS, vol 3829. Springer, Berlin, pp 196–210

    Google Scholar 

  13. D’Souza D (2000) A logical study of distributed timed automata. PhD thesis, BITS Pilani

  14. D’Souza D (2003) A logical characterisation of event clock automata. Int J Found Comput Sci 14(4):625–640

    Article  MathSciNet  MATH  Google Scholar 

  15. D’Souza D, Thiagarajan PS (1999) Product interval automata: a subclass of timed automata. In: FSTTCS. LNCS, vol 1738. Springer, Berlin, pp 60–71

    Google Scholar 

  16. Elgot CC (1961) Decision problems of finite automata design and related arithmetics. Trans Am Math Soc 98:21–52

    Article  MathSciNet  Google Scholar 

  17. Genest B, Kuske D, Muscholl A (2006) A Kleene theorem and model checking algorithms for existentially bounded communicating automata. Inf Comput 204(6):920–956

    Article  MathSciNet  MATH  Google Scholar 

  18. Godefroid P (1996) Partial-order methods for the verification of concurrent systems—an approach to the state-explosion problem. LNCS, vol 1032. Springer, Berlin

    Book  Google Scholar 

  19. Henriksen JG, Mukund M, Narayan Kumar K, Sohoni M, Thiagarajan PS (2005) A theory of regular MSC languages. Inf Comput 202(1):1–38

    Article  MathSciNet  MATH  Google Scholar 

  20. Krcal P, Yi W (2006) Communicating timed automata: the more synchronous, the more difficult to verify. In: CAV. LNCS, vol 4144. Springer, Berlin, pp 243–257

    Google Scholar 

  21. Narayan Kumar K (2012) The theory of MSC languages. In: D’Souza D, Shankar P (eds) Modern Applications of Automata Theory. IISc Res Monographs, vol 2. World Scientific, Singapore, pp 289–324

    Chapter  Google Scholar 

  22. Lohrey M, Muscholl A (2004) Bounded MSC communication. Inf Comput 189(2):160–181

    Article  MathSciNet  MATH  Google Scholar 

  23. Ramchandani C (1974) Analysis of asynchronous concurrent systems by timed Petri nets. PhD thesis, Massachusetts Institute of Technology

Download references

Acknowledgements

We thank the anonymous referees for their constructive suggestions which helped in improving the presentation of the paper.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to S. Akshay.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Akshay, S., Bollig, B. & Gastin, P. Event clock message passing automata: a logical characterization and an emptiness checking algorithm. Form Methods Syst Des 42, 262–300 (2013). https://doi.org/10.1007/s10703-012-0179-8

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10703-012-0179-8

Keywords

Navigation