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Time-triggered runtime verification

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Abstract

The goal of runtime verification is to monitor the behavior of a system to check its conformance to a set of desirable logical properties. The literature of runtime verification mostly focuses on event-triggered solutions, where a monitor is invoked when an event of interest occurs (e.g., change in the value of some variable). At invocation, the monitor evaluates the set of properties of the system that are affected by the occurrence of the event. This constant invocation introduces two major defects to the system under scrutiny at run time: (1) significant overhead, and (2) unpredictability of behavior. These defects are serious obstacles when applying runtime verification on safety-critical systems that are time-sensitive by nature.

To circumvent the aforementioned defects in runtime verification, in this article, we introduce a novel time-triggered approach, where the monitor takes samples from the system with a constant frequency, in order to analyze the system’s health. We describe the formal semantics of time-triggered monitoring and discuss how to optimize the sampling period using minimum auxiliary memory. We show that such optimization is NP-complete and consequently introduce a mapping to Integer Linear Programming. Experiments on a real-time benchmark suite show that our approach introduces bounded overhead and effectively reduces the involvement of the monitor at run time by using negligible auxiliary memory. We also show that in some cases it is even possible to reduce the overall overhead of runtime verification by using our time-triggered approach when the structure of the system allows choosing a long enough sampling period.

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Notes

  1. To access the tool, please visit http://uwaterloo.ca/embedded-software-group/projects/rithm.

  2. In Sect. 3, we will compute the longest sampling period of a CFG based on BCET of basic blocks. This computation is quite realistic, as (1) all hardware vendors publish the BCET of their instruction set in terms of clock cycles, and (2) BCET is a conservative approximation and no execution occurs faster than that.

  3. To access the tool, please visit http://uwaterloo.ca/embedded-software-group/projects/rithm.

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Acknowledgements

This research was supported in part by NSERC Discovery Grant 418396-2012, NSERC DG 357121-2008, ORF-RE03-045, ORF-RE04-036, ORF-RE04-039, APCPJ 386797-09, CFI 20314 and CMC, STPGP-430575, and the industrial partners associated with these projects.

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Authors and Affiliations

  1. School of Computer Science, University of Waterloo, 200 University Avenue West, Waterloo, ON, Canada, N2L 3G1

    Borzoo Bonakdarpour

  2. Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, ON, Canada, N2L 3G1

    Samaneh Navabpour & Sebastian Fischmeister

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  1. Borzoo Bonakdarpour
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  2. Samaneh Navabpour
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  3. Sebastian Fischmeister
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Correspondence to Borzoo Bonakdarpour.

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Bonakdarpour, B., Navabpour, S. & Fischmeister, S. Time-triggered runtime verification. Form Methods Syst Des 43, 29–60 (2013). https://doi.org/10.1007/s10703-012-0182-0

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