Abstract
This paper presents the formal verification of start-up for a differential ring-oscillator circuit used in industrial designs. We present an efficient algorithm for finding DC equilibria to establish a condition that ensure the oscillator is free from lock-up. Further, we present a formal verification solution for the problem. Using dynamical systems theory, we show that any oscillator must have a non-empty set of states from which it fails to start properly. However, it is possible to show that these failures only occur with zero probability. To do so, this paper generalizes the “cone argument” initially presented in (Mitchell and Greenstreet, in Proceedings of the third workshop on designing correct circuits, 1996) and proves the soundness of this generalization. This paper also shows how concepts from analog design such as differential operation can be soundly incorporated into the verification to produce simpler models and reduce the complexity of the verification task.
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig1_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig2_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig3_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig4_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig5_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig6_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig7_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig8_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig9_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig10_HTML.gif)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10703-013-0204-6/MediaObjects/10703_2013_204_Fig11_HTML.gif)
Similar content being viewed by others
References
Althoff M, Rajhans A et al. (2011) Formal verification of phase-locked loops using reachability analysis and continuization. In: Proceedings of the 2011 international conference on computer aided design, pp 659–666
Boyd S, Vandenberghe L (2004) Convex optimization. Cambridge University Press, Cambridge
Cao Y (2008) PTM: predictive technology model. http://ptm.asu.edu
Chaney TJ, Molnar CE (1973) Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans Comput C-22(4):421–422
Djahanshahi H, Salama CAT (2000) A two-stage differential CCO implementation in submicron CMOS. In: Proceedings of the 43rd IEEE Midwest symposium on circuits and systems, pp 294–297
Fränzle M (2007) HySAT: an efficient proof engine for bounded model checking of hybrid systems. Form Methods Syst Des 30(3):179–198. doi:10.1007/s10703-006-0031-0
Frehse G (2005) PHAVer: algorithmic verification of hybrid systems past HyTech. In: Proceedings of the fifth international workshop on hybrid systems: computation and control. LNCS, vol 3414. Springer, Berlin, pp 258–273
Frehse G, Krogh BH, Rutenbar RA (2006) Verifying analog oscillator circuits using forward/backward abstraction refinement. In: Proceedings of design automation and test Europe, pp 257–262
Greenstreet MR, Yang S (2008) Verifying start-up conditions for a ring oscillator. In: Proceedings of the 18th great lakes symposium on VLSI (GLSVLSI’08), pp 201–206
Gupta S, Krogh BH, Rutenbar RA (2004) Towards formal verification of analog designs. In: Proceedings of 2004 IEEE/ACM international conference on computer aided design, pp 210–217
Hartong W, Heidrich L, Barke E (2002) Model checking algorithms for analog verification. In: Proceedings of the 39th ACM/IEEE design automation conference, pp 542–547
Henzinger TA, Ho P-H, Wong-Toi H (1998) Algorithmic analysis of nonlinear hybrid systems. IEEE Trans Autom Control 43(4):540–554
Heydari P, Pedram M (2001) Jitter-induced power/ground noise in CMOS PLLs: a design perspective. In: Proceedings international conference on computer design (ICCD), pp 209–213
Hirsch MW, Smale S (1974) Differential equations, dynamical systems, and linear algebra. Academic Press, San Diego
Jones KD, Kim J, Konrad V (2008) Some “real world” problems in the analog and mixed-signal domains. In: Proc workshop on designing correct circuits
Kim J, Jeeradit M, Lim B, Horowitz MA (2009) Leveraging designer’s intent: a path toward simpler analog CAD tools. In: Proceedings of the custom integrated circuits conference (CICC’2009), pp 613–620. doi:10.1109/CICC.2009.5280741
Kinniment DJ, Dike C et al. (2007) Measuring deep metastability and its effect on synchronizer performance. IEEE Trans Very Large Scale Integr (VLSI) Syst 15:1028–1039
Little S, Myers C (2008) Abstract modeling and simulation aided verification of analog/mixed-signal circuits, Princeton, NJ, presented at the 2008 Workshop on Formal Verification for Analog Circuits (FAC’08)
Little S, Seegmiller N, Walter D, Myers C, Yoneda T (2006) Verification of analog/mixed-signal circuits using labeled hybrid Petri nets. In: Proceedings of the international conference on computer aided design, pp 275–282
Mitchell I, Greenstreet M (1996) Proving Newtonian arbiters correct, almost surely. In: Proceedings of the third workshop on designing correct circuits, Båstad, Sweden
Moura L, Bjørner N (2008) Z3: an efficient SMT solver. In: Ramakrishnan CR, Rehof J (eds) Tools and algorithms for the construction and analysis of systems. Lecture notes in computer science, vol 4963. Springer, Berlin, pp 337–340. 978-3-540-78799-0
Nissinen I, Mantyniemi A, Kostamovaara J (2003) A CMOS time-to-digital converter based on a ring oscillator for a laser radar. In: Proceedings of the 29th European solid-state circuits conference (ESSCIRC’03), pp 469–472
Park C-H, Kim B (1999) A low-noise, 900MHz VCO in 0.6 μ CMOS. IEEE J Solid-State Circuits 34(5):586–591
Pollard D (2001) A user’s guide to measure theoretic probability. Cambridge University Press, Cambridge
Rump SM (1999) INTLAB - INTerval LABoratory. In: Csendes T (ed) Developments in reliable computing. Kluwer Academic Publishers, Dordrecht, pp 77–104. http://www.ti3.tu-harburg.de/rump/
Rump SM (2006) Eigenvalues, pseudospectrum and structured perturbations. Linear Algebra Appl 413(1–2):567–593. doi:10.1016/j.laa.2005.06.009
Steinhorst S, Hedrich L (2012) Trajectory-directed discrete state space modeling for formal verification of nonlinear analog circuits. In: 2012 IEEE/ACM international conference on computer-aided design (ICCAD), pp 202–209
Steinhorst S, Peter M, Hedrich L (2009) State space exploration of analog circuits by visualized multi-parallel particle simulation. In: International conference on signal processing systems (ICSPS’09), pp 858–862
Tatschl-Unterberger E, Cyrusian S, Ruegg M (2005) A 2.5 GHz phase-switching PLL using a supply controlled 2-delay-stage 10 GHz ring oscillator for improved jitter/mismatch. In: IEEE international symposium on circuits and systems (ISCAS), pp 5453–5456
Tiwari SK, Gupta A et al (2008) fSpice: a Boolean satisfiability based approach for formally verifying analog circuits, Princeton, NJ, presented at the 2008 Workshop on Formal Verification for Analog Circuits (FAC’08)
Tiwari SK, Gupta A et al. (2010) First steps towards SAT-based formal analog verification. In: Proceedings of the 2010 international conference on computer aided design
Xiao J, Peterchev AV, Sanders SR (2001) Architecture and IC implementation of a digital VRM controller. In: IEEE 32nd annual power electronics specialists conference (PESC’01), vol 1, pp 38–47
Yan C, Greenstreet MR (2008) Faster projection based methods for circuit-level verification. In: Proceedings of the 2008 Asia and South Pacific design automation conference (ASPDAC’08), pp 410–415
Zaki MH, Mitchell I, Greenstreet MR (2009) Towards a formal analysis of DC equilibria of analog designs, Grenoble, France. Presented at the 2009 Workshop on Formal Verification for Analog Circuits (FAC’09)
Acknowledgements
Throughout this work we have benefited from interactions with many excellent colleagues. We would like to express our particular gratitude to Michael Friedlander, Kevin Jones, Victor Konrad, Ian Mitchell, John Poulton, and Mohamed Zaki for helpful conversations and inspiration in the course of this research. Mitchell
Author information
Authors and Affiliations
Corresponding author
Additional information
This work was supported in part by grants from Intel, Oracle, and the Natural Sciences and Engineering Research Council of Canada.
Rights and permissions
About this article
Cite this article
Yan, C., Greenstreet, M.R. & Yang, S. Verifying global start-up for a Möbius ring-oscillator. Form Methods Syst Des 45, 246–272 (2014). https://doi.org/10.1007/s10703-013-0204-6
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10703-013-0204-6