Abstract
We present a novel approach for solving quantified bit-vector constraints in Satisfiability Modulo Theories (SMT) based on computing symbolic inverses of bit-vector operators. We derive conditions that precisely characterize when bit-vector constraints are invertible for a representative set of bit-vector operators commonly supported by SMT solvers. We utilize syntax-guided synthesis techniques to aid in establishing these conditions and verify them independently by using several SMT solvers. We show that invertibility conditions can be embedded into quantifier instantiations using Hilbert choice expressions and give experimental evidence that a counterexample-guided approach for quantifier instantiation utilizing these techniques leads to performance improvements with respect to state-of-the-art solvers for quantified bit-vector constraints.
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Notes
Note that this makes this theory complete in the sense of Sect. 2.2.
That is, provided that s is equivalent to a term of the form \(2_{[n]} \cdot s' + 1_{[n]} \).
Available at https://cvc4.cs.stanford.edu/papers/CAV2018-QBV/
Note that \(\psi \) may have free variables besides those in \(\varvec{x} \) which are then also free variables of \(\varphi \).
Note that in order for a selection function that is finite on x and \(\psi \) to also be monotonic on the same, it must be the case that \(\bigwedge _{\varvec{t} \in {\mathcal {S}}^*}\psi [t]\ T\)-entails \(\psi \), so that no more legal inputs exist by the time the set \({\mathcal {S}}^*\) is exhausted.
We evaluate the effectiveness of these configurations in Sect. 5.
This is a simple heuristic to generate literals that can be solved for \(x_i\). More elaborate heuristics could be used in practice.
We are using \(x_1 \cdot a>_\mathrm {u} b\) here instead of \(\lnot (x_1 \cdot a \le _\mathrm {u} b)\) for conciseness.
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This work was partially supported by DARPA under awards FA8750-15-C-0113 and FA8650-18-2-7861 and by the National Science Foundation under award 1656926.
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Niemetz, A., Preiner, M., Reynolds, A. et al. On solving quantified bit-vector constraints using invertibility conditions. Form Methods Syst Des 57, 87–115 (2021). https://doi.org/10.1007/s10703-020-00359-9
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DOI: https://doi.org/10.1007/s10703-020-00359-9