Abstract
Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical Spice simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results show improvements in both the speed and power of the optimised standard cells and that the impact of threshold voltage variation is reduced.
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Acknowledgments
The authors would like to thank the editors and reviewers for their comments and suggestions to improve the quality of this paper. The authors would like to thank all partners of the EPSRC funded Nano-CMOS project (ref: EP/E001610/1).
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Walker, J.A., Hilder, J.A., Reid, D. et al. The evolution of standard cell libraries for future technology nodes. Genet Program Evolvable Mach 12, 235–256 (2011). https://doi.org/10.1007/s10710-011-9131-8
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DOI: https://doi.org/10.1007/s10710-011-9131-8