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An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications

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Abstract

As processor technology continues to advance at a rapid pace, the principal performance bottleneck of shared memory systems has become the memory access latency. In order to understand the effects of cache and memory hierarchy on system latencies, performance analysts perform benchmark analysis on existing multiprocessors. In this study, we present a detailed comparison of two architectures, the HP V-Class and the SGI Origin 2000. Our goal is to compare and contrast design techniques used in these multiprocessors. We present the impact of processor design, cache/memory hierarchies and coherence protocol optimizations on the memory system performance of these multiprocessors. We also study the effect of parallelism overheads such as process creation and synchronization on the user-level performance of these multiprocessors. Our experimental methodology uses microbenchmarks as well as scientific applications to characterize the user-level performance. Our microbenchmark results show the impact of Ll/L2 cache size and TLB size on uniprocessor load/store latencies, the effect of coherence protocol design/optimizations and data sharing patterns on multiprocessor memory access latencies and finally the overhead of parallelism. Our application-based evaluation shows the impact of problem size, dominant sharing patterns and number of Processors used on speedup and raw execution time. Finally, we use hardware counter measurements to study the correlation of system-level performance metrics and the application’s execution time performance.

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Authors and Affiliations

  1. Intel Corporation, USA

    Ravi Iyer

  2. Parasol Laboratory, Department of Computer Science, Texas A&M University, College Station, TX, 77843-3112, USA

    Jack Perdue, Lawrence Rauchwerger & Nancy M. Amato

  3. Department of Computer Science and Engineering, University of California Riverside, Riverside, CA, 92521, USA

    Laxmi Bhuyan

Authors
  1. Ravi Iyer
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  2. Jack Perdue
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  3. Lawrence Rauchwerger
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  4. Nancy M. Amato
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  5. Laxmi Bhuyan
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Corresponding author

Correspondence to Lawrence Rauchwerger.

Additional information

preliminary version of this paper appeared in the 13th ACM International Conference on Supercomputing (ICS’99).(13) This work was done while Iyer and Bhuyan were at Texas A&M. It was supported in part by a Hewlett-Packard Equipment Grant. Amato and Rauchwerger supported in part by NSF Grants ACI-9872126, EIA-9975018, EIA-0103742, EIA-9805823, ACR-0081510, ACR-0113971, CCR-0113974, EIA-9810937, EIA-0079874, by the DOE ASCI ASAP program, and by the Texas Higher Education Coordinating Board grant ATP-000512-0261-2001. Perdue supported in part by a Dept. of Education Graduate Fellowship (GAANN)

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Iyer, R., Perdue, J., Rauchwerger, L. et al. An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications. Int J Parallel Prog 33, 307–350 (2005). https://doi.org/10.1007/s10766-004-1187-0

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  • DOI: https://doi.org/10.1007/s10766-004-1187-0

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