Aggressive prefetching mechanisms improve performance of some important applications, but substantially increase bus traffic and “pressure” on cache tag arrays. They may even reduce performance of applications that are not memory bounded. We introduce a “feedback” mechanism, termed Prefetcher Assessment Buffer (PAB), which filters out requests that are unlikely to be useful. With this, applications that cannot benefit from aggressive prefetching will not suffer from their side-effects. The PAB is evaluated with different configurations, e.g., “all L1 accesses trigger prefetches” and “only misses to L1 trigger prefetches”. When compared with the non-selective concurrent use of multiple prefetchers, the PAB’s application to prefetching from main memory to the L2 cache can reduce the number of loads from main memory by up to 25% without losing performance. Application of more sophisticated techniques to prefetches between the L2- and L1-cache can increase IPC by 4% while reducing the traffic between the caches 8-fold.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Smith A.J. (Sep. 1982). Cache Memories. Computing Surveys 14(3):473–530
Chen T.F. and Baer J.L. (Nov. 1991) An Effective On-chip Preloading Scheme to Reduce Data Access Penalty. Proceedings of Supercomputing 91:176–186
Intel Co.: Intel Pentium 4 and Intel Xeon Processor Optimization, http://cache-www. intel.com/cd/00/00/01/76/17672_24896607.pdf or developer.intel.com.
Apple Computer, Inc., Technical note TN2087: PowerPC G5 Performance Primer, http:// developer.apple.com/technotes/tn/tn2087.html.
Vanderwiel S.P. and Lijia D.J. (Jun. 2000). Data Prefetch Mechanisms. ACM Computing Surveys 32(2): 174–199
Tse J. and Smith A.J. (May 1998). CPU Cache Prefetching: Timing Evaluation of Hardware Implementations. IEEE Transactions on Computers 47(5):509–526
C. J. Hughes and S. V. Adve, Memory-Side Prefetching for Linked Data Structures, Technical Report UIUCDCS-R-2001–2221, Univ. or Illinois UC (May 2001).
M. Karlson, F. Magnus, and P. Stenstrom, A Prefetching Technique for Irregular Accesses to Linked Data Structures, Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA), pp. 206–217 (Jan. 2000).
N. Kohout, S. Choi, D. Kim, and D. Yeung, Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism For Pointer-Chasing Codes, Proceedings of yhe International Conference on Parallel Architectures and Compilation Techniques, pp. 268–279 (Sep. 2001).
Chiu J.C., Chi S.A., and Chung C.P. (Sep. 1999). Instruction Cache Prefetching Directed by Branch Prediction. IEE Proceedings – Computers & Digital Techniques 146(5):241–246
Luk C-K. and Mowry T.C. (Feb. 2001). Architectural and Compiler Support for Effective Instruction Prefetching: A Cooperative Approach. ACM Transactions on Computer Systm 19(1):71–109
Manku G.S., Prasad M.R., and Patterson D.A. A New Voting Based Hardware Data Prefetch Scheme, Proceedings of the 4th International Conference on High Performance Computing, pp. 100–105 (Dec. 1997).
Johnson T.L., Connors D.A., and Hwu W-M.W. (1998). Run-time Adaptive Cache management. Proceedings of the 31st Hawaii International Conference on System Sciences vol. 7, pp. 774–775
A. Ki and A. E. Knowles, Adaptive Data Prefetching Using Cache Information, Proceedings 11th International Conference on Supercomputing, pp. 204–212 (1997).
R. Pendse and H. Katta, Selective Prefetching: Prefetching when Only Required, Proceedings of the 42nd Midwest Symposium on Circuits and Systems, vol. 2, pp. 866–869 (Aug. 1999).
P. Reungsang, S. K. Park, G. Lee, S. -W. Jeong, and H. -L. Roh, Reducing Cache Pollution of Prefetching in a Small Data Cache, Procedings of the International Conference on Computer Design (ICCD), pp. 530–533 (Sep. 2001).
IBM, POWER-3: Next generation 64-bit PowerPC Processor Design, www-1.ibm.com/ servers/eserver/pseries/hardware/whitepapers/power3wp.html.
Cristal A., Santana O.J., Valero M., and Martinez J.F. (2004). Toward Kilo-Instruction Processors. ACM Transactions Architech and Code Opt. 1: 289–417
J. W. Fu, J. H. Patel, and B. L. Jansen, Stride Directed Prefetching in Scalar Processors, Proceedings of the International Symposium on Microarchitecture (MICRO-25), pp. 102–110 (Dec. 1992).
I. Sklenar, Prefetch Unit for Vector Operation on Scalar Computers, Proceedings 19th International Symposium on Computer Architecture (ISCA), pp. 31–37 (May 1992).
H. Yu and G. Kedem, DRAM-page Based Data Prediction and Prefetching, Proceedings International Conference on Computer Design (ICCD), pp. 267–275 (Sep. 2000).
Chen T.F. and Baer J.L. (May 1995). Effective Hardware-Based Data Prefetching for High Performance Processors. IEEE Transaction on Computers 44(5): 609–623
J. F. Cantin and M. D. Hill, Cache Performance for SPEC CPU2000 Benchmarks, http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data/.
Austin T., Larson E., and Ernst D. (Feb. 2002). SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer 35(2): 59–67
A. Gendler, Efficient Multi-Prefetcher Architectures using a Prefetcher Assessment Buffer (PAB), MSc Dissertation, Electrical Eng. Dept., Technion (2005).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Gendler, A., Mendelson, A. & Birk, Y. A PAB-Based Multi-Prefetcher Mechanism. Int J Parallel Prog 34, 171–188 (2006). https://doi.org/10.1007/s10766-006-0006-1
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10766-006-0006-1