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Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory

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This paper presents a low-power tag organization for physically tagged caches in embedded processors with virtual memory support. An exceedingly small subset of tag bits is identified for each application hot-spot so that only these tag bits are used for cache access with no performance sacrifice as they provide complete address resolution. The minimal subset of physical tag bits is dynamically updated following the changes in the physical address space of the application. Operating system support is introduced in order to maintain the reduced tags during program execution. Efficient algorithms are incorporated within the memory allocator and the dynamic linker in order to achieve dynamic update of the reduced tags. The only hardware support needed within the I/D-caches is the support for disabling bitlines of the tag arrays. An extensive set of experimental results demonstrates the efficacy of the proposed approach.

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Authors and Affiliations

  1. ECE Department, University of Maryland, 1421 A.V. Williams Build., College Park, MD, 20742, USA

    Peter Petrov

  2. University of California, San Diego, CA, USA

    Alex Orailoglu

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  1. Peter Petrov
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  2. Alex Orailoglu
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Correspondence to Peter Petrov.

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Petrov, P., Orailoglu, A. Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory. Int J Parallel Prog 35, 157–177 (2007). https://doi.org/10.1007/s10766-006-0030-1

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  • DOI: https://doi.org/10.1007/s10766-006-0030-1

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