Skip to main content
Log in

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

  • Published:
International Journal of Parallel Programming Aims and scope Submit manuscript

Abstract

Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. IEEE Standard for Local and Metropolitan Area Networks—Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems—Draft Amendment j: Multihop Relay Specification, IEEE P802.16j/D2 (2007, December 24)

  2. Schneider, A., Knäblein, J., Müller, B., Putsche, M., Goller, S., Pross, U., Heinkel, U.: Ethernet based in-service reconfiguration of SoCs in telecommunication networks. In: 4th Workshop on Dynamically Reconfigurable Systems (DRS), Zürich (2007, March)

  3. do Carmo Lucas, A., et al.: A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. In: Proceedings of of the Conference on Design, Automation and Test in Europe (DATE’06), pp. 194–199 (2006)

  4. Mucci, C., Vanzolini, L., Deledda, A., Campi, F., Gaillat, G.: Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection. In: Proceedings of the International Symposium on System-on-Chip, pp. 1–4 (2007)

  5. Compton K., Hauck S.: Reconfigurable computing: a survey of systems and software. ACM Computing Surveys (CSUR) 34(2), 171–210 (2002)

    Article  Google Scholar 

  6. Wu, K., Tsai, Y.: Structured ASIC, evolution or revolution? In: Proceedings of the 2004 International Symposium on Physical Design (ISPD‘04), pp. 103–106. ACM, New York

  7. DeHon, A.: Balancing interconnect and computation in a reconfiguable computing array (or, why you don’t really want 100% LUT utilization). In: Proceedings of FPGA 1999, pp. 69–78 (1999)

  8. Virtex-5 Family Overview, data sheet, Xilinx (2008, September 23)

  9. Stratix IV Device Handbook, Altera, vol. 1, version 2.0 (2008, November)

  10. Achieving Higher System Performance with the Virtex-5 Family of FPGAs. White paper, Xilinx, v1.1.1 (2006, July 7)

  11. Ebeling C., Fisher C., Xing G., Shen M., Liu H.: Implementing an OFDM receiver on the RaPiD reconfigurable architecture. IEEE Trans. Comput. 53(11), 1436–1448 (2004)

    Article  Google Scholar 

  12. Singh, H., Lee, M.-H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Chaves Filho, E.M.: MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. Comput. (2000, May)

  13. Zhang, H., et al.: A 1V Heterogeneus Reconfigurable Processor IC for Baseband Wireless Applications, pp. 68–69. ISSCC Dig. Tech. Papers (2000)

  14. Sato, T., Watanabe, H., Shiba, K.: Implementation of dynamically reconfigurable processor DAPDNA-2. In: Proceedings of VLSI Design, Automation and Test, pp. 323–324 (2005)

  15. Goldstein, S.C., Schmit, H., Budiu, M., Cadambi, S., Moe, M., Reed Taylor, R.: PipeRench: a reconfigurable architecture and compiler. In: IEEE Computer (2000, April)

  16. Cherepacha, D., Lewis, D.: A datapath oriented architecture for FPGAs. In: Proceedings of FPGA’94 (1994)

  17. Bedford Taylor, M., et al.: Evaluation of the Raw microprocessor: an exposed-wire delay architecture for ILP and streams. In: Proceedings of 31th Annual International Symposium on Computer Architectures (ISCA), pp. 2–13 (2004)

  18. Hauser, J.R., Wawrzynek, J.: Garp: a MIPS processor with a configurable coprocessor. In: Proceedings of FPGAs for Custom Computing Machines, pp. 12–21 (1997)

  19. Mei, B., Vernalde, S., Verkest, D., DeMan, H., Lauwereins, R.: ADRES: an architecture with tightly coupled VLIW processor and corse-Grained reconfigurable matrix. In: Proceedings of FPL 2003

  20. XPP-III Processor Overview. White paper, PACT XPP Technologies, 2006. Available: http://www.pactxpp.com

  21. Campi, F., et al.: A dynamically adaptive DSP for heterogeneous reconfigurable platforms. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE’07) (2007)

  22. Baron, M.: M2000’s Spherical FPGA Cores. In: MicroProcessor Report (2004, December)

  23. ARM926EJ-STM Technical Reference Manual (Revision r0p5). ARM Ltd (2008)

  24. Vassiliadis, S., Bertels, K., Kuzmanov, G., et al.: The MOLEN polymorphic processor. Proc. IEEE Trans. Comput. 53(11) (2004)

  25. Coppola, M., Locatelli, R., Maruccia, G., Pieralisi, L., Scandurra, A.: Spidergon: a novel on-chip communication network. In: Proceedings of the International Symposium on System-on-Chip, pp. 16–18 (2004)

  26. Whitty, S., Ernst, R.: A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture. In: Proceedings of the IEEE Parallel and Distributed Processing Symposium (IPDPS) (2008)

  27. Chevobbe, S., Guyetant, S.: Reducing reconfiguration overheads in heterogeneous multi-core RSoCs with predictive configuration management. Recosoc (2008)

  28. AMBA Specification (Rev 2.0). ARM Ltd (2001)

  29. Bartic, T.A., et.al.: Topology adaptive NoC design and implementation. In: IEE Computers and Digital Techniques (2005, July)

  30. PACT Software Design System XPP-IIb (PSDS XPP-IIb)—Programming Tutorial. PACT XPP Technologies, version 3.2, 2005. Available: http://www.xpp.com

  31. Flexeos Software User Manual, version 2.4.4, M2000 (2006)

  32. Mucci, C., et al.: A C-based algorithm development flow for a reconfigurable processor architecture. In: IEEE SOC, Tampere (2003)

  33. Gao, G., Wong, Y., Ning, Q.: A timed petri-net model for fine-grain loop scheduling. In: ACM SIGPLAN (1991, June)

  34. Lenormand, E., Edelin, G.: An industrial perspective: pragmatic high-end signal processing environment at Thales. In: 3rd International Workshop on Synthesis, Architectures, Modeling and Simulation, SAMOS (2003)

  35. CriticalBlue: Boosting Software Processing Performance With Coprocessor Synthesis. White paper (2005)

  36. Cambonie, J., Guérin, S., Keryell, R., Lagadec, L., Pottier, B., Sentieys, O., Weber, B., Yazdani, S.: Compiler and system techniques for soc distributed reconfigurable accelerators. In: Proceedings of SAMOS 2004, pp. 293–302 (2004)

  37. CoSy Compilers Overview of Construction and Operation. White paper, ACE (2003, April)

  38. Moscu Panainte, E., Bertels, K., Vassiliadis, S.: The Molen Compiler for Reconfigurable Processors. ACM Transactions in Embedded Computing Systems (TECS) 6(1) (2007, February)

  39. Moscu Panainte, E., Bertels, K., Vassiliadis, S.: Instruction scheduling for dynamic hardware configurations. In: Proceedings of Design, Automation and Test in Europe 2005 (DATE 05), pp. 100–105, Munich (2005, March)

  40. eCos Reference Manual. Available http://ecos.sourceware.org/docs-latest/ref/ecos-ref.html

  41. Rossi, D., Campi, F., Deledda, A., Spolzino, S., Pucillo, S.: A heterogeneous digital signal processor implementation for dynamically reconfigurable computing. In: IEEE 2009 Custom Integrated Circuits Conference (CICC) (2009)

  42. Whitty, S., Sahlbach, H., Putzke-Röming, W., Ernst, R.: Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. In: Proceedings of Design, Automation and Test in Europe (DATE) (2009)

  43. Whitty, S., Sahlbach, H., Hurlburt, B., Putzke-Röming, W., Ernst, R.: Application-specific memory performance of a heterogeneous reconfigurable architecture. In: Proceedings of Design, Automation and Test in Europe (DATE’2010) (to appear)

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Arnaud Grasset.

Additional information

This work was supported in part by the European Union in the 6th R&D Framework Program (MORPHEUS IST project, number 027342).

Rights and permissions

Reprints and permissions

About this article

Cite this article

Grasset, A., Millet, P., Bonnot, P. et al. The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform. Int J Parallel Prog 39, 328–356 (2011). https://doi.org/10.1007/s10766-010-0160-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10766-010-0160-3

Keywords

Navigation