Abstract
The new emergence of data-intensive applications raises a huge requirement on the capacity of memory. However, an obvious increase of memory makes the corresponding energy consumption unacceptable in practice. To address this question, any effort only to reduce the energy consumption of dynamic random access memory (DRAM) is ineffective. Recently, combining DRAM and phase change memory (PCM) to construct a hybrid main memory is recognized as a promising solution to distinctly reduce the energy consumption. In this paper, we propose a new page-level energy management strategy to optimize the energy consumption of the hybrid main memory. The proposed strategy records pages’ local and global access information by a new data structure, and then classifies pages by the access history, at last adaptively places PCM or DRAM pages according to the memory characteristics and remaps the migrated pages. Our experimental results show that our strategy can achieve 9.4 % of energy saving and 9.6 % of performance improvement at most compared with APG and PDRAM, which were proposed respectively by conferences RACS’12 and DAC’09.
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References
Zhou, P., Zhao, B., Yang, J., Zhang, Y.: A durable and energy efficient main memory using phase change memory technology. In: Proceedings of the 46th Annual Design Automation Conference, pp. 14–23. ACM (2009)
Chung, L.: Phase change memory. Sci. China (Inf. Sci.) 2011(5), 1061–1072 (2011)
Dhiman, G., Ayoub, R., Rosing, T.: PDRAM: a hybrid PRAM and DRAM main memory system. In: Proceedings of the 46th Annual Design Automation Conference, pp. 664–469. ACM (2009)
Qureshi, M.K., Srinivasan, V., Rivers, J.A.: Scalable high performance main memory system using phase-change memory technology. In: Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 24–33. ACM (2009)
Mangalagiri, P., Sarpatwari, K., Yanamandra, A., Narayanan, V., Xie, Y., Irwin, M.J. Karim, O.A.: A low-power phase change memory based hybrid cache architecture. In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI, pp. 395–398. ACM (2008)
Park, H., Yoo, S., Lee, S.: Power management of hybrid DRAM/PRAM-based main memory. In: Proceedings of the 48th Design Automation Conference, pp. 59–64. ACM (2011)
Baek, S., Lee, H.G., Nicopoulos, C., Kim, J.: A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures. In: Proceedings of the Great Lakes Symposium on VLSI, pp. 345–350. ACM (2012)
Qureshi, M.K., Karidis, J., Franceschini, M. Srinivasan, V. Lastras, L. Abali, B.: Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 14–23. ACM (2009)
Ferreira, A.P., Zhou, M., Bock, S.: Childers, B., Melhem, R., Mossé, D.: Increasing PCM main memory lifetime. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’10, pp. 914–919. European Design and Automation Association (2010)
Shin, D.-J., Park, S.K., Kim, S.M., Park, K.H.: Adaptive page grouping for energy efficiency in hybrid PRAM-DRAM main memory. In: Proceedings of the 2012 ACM Research in Applied Computation Symposium, pp. 395–402. ACM (2012)
Ramos, L.E., Gorbatov, E., Bianchini, R.: Page placement in hybrid memory systems. In: Proceedings of the International Conference on Supercomputing, pp. 85–95. ACM (2011)
Lee, B.C., Ipek, E., Mutlu, O., Burger, D.: Phase change memory architecture and the quest for scalability. Commun. ACM 53(7), 99–106 (2010)
Binkert, N., Dreslinski, R., Hsu, L., Lim, K., Saidi, A., Reinhardt, S.: The M5 simulator: modeling networked systems. IEEE Micro 26(4), 52–60 (2006)
Poremba, M., Xie, Y.: Nvmain: an architectural-level main memory simulator for emerging non-volatile memories. In: Proceedings of the 2012 IEEE Annual Symposium on VLSI, pp. 392–397. IEEE (2012)
Lee, S., Bahn, H., Noh, S.: Clock-dwf: a write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures. IEEE Trans. Comput. 63(9), 2187–2200 (2014)
Acknowledgments
This paper is supported by China National Natural Science Foundation under Grants Nos. 61322210, 61379135, Doctoral Fund of Ministry of Education of China under Grant No. 20130142110048, National High-tech Research and Development Program of China (863 Program) under Grant No. 2015AA015303.
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Zhang, J., Liao, X., Jin, H. et al. An Optimal Page-Level Power Management Strategy in PCM–DRAM Hybrid Memory. Int J Parallel Prog 45, 4–16 (2017). https://doi.org/10.1007/s10766-015-0382-5
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DOI: https://doi.org/10.1007/s10766-015-0382-5