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Generating ASIPs with Reduced Number of Connections to the Register-File

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Abstract

We propose automatic synthesis of application specific instruction set processors (ASIPs). We use pipeline execution of multi-op machine-instructions, e.g., \(*({ reg}1*{ reg}2) = (*{ reg}3)+(*{ reg}4)\) (C-syntax) an instruction with three memory pipeline stages and two arithmetic stages. The problem is, for a given set of loops, to find a pipeline configuration and a multi-op ISA that maximizes the IPC (instructions per cycle) while minimizing the resource usage and the cost of interconnections to the register-file of the resulting CPU. The algorithm is based on finding an efficient cover of a large graph by a small set of convex sub-graphs (called \(g_i\)s) that are consistent with a given set of pipeline units. Unlike previous works, \(g_i\)s are not synthesized to circuits that are executed in a co-processor mode but rather both \(g_i\)s and the rest of the program are executed by the same set of multiop pipeline units. In this way we eliminate the overhead associated with the co-processor mode of regular ASIPs but maintain high values of IPC of these ASIPs. The main advantage of using pipeline execution of multi-op versus VLIW instructions is shown to be the cost of interconnections between the CPU’s execution units and the register file. Once the pipeline configuration and the cover \(g_1 \cup \cdots \cup g_n=G\) has been computed the Verilog RTL of the corresponding CPU (extended with branch instructions) is generated and synthesized to FPGA. The results show that, for a set of selected kernels, the resulting ASIP (called Ocpu) obtains higher IPC values compare to an equivalent compilation to an ARM cpu while obtaining similar clock frequencies.

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Notes

  1. Using Vivado \(+\) Kintex-7 we compared the Ocpu \(p=2\) \(\hbox {k}=5\) with Amber (A free clone of ARM-7) and obtained that the Ocpu required 4.73 versus 1.2 W for the Amber cpu. This is reasonable as the Ocpu contains 10times more functional operations than the Amber.

  2. Using a similar technique to the one used in Dilworth’s theorem [13] wherein it was shown that a DAG G of width K (analogue to a VLIW execution) can be covered by K chains (analog to a pipeline execution).

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Authors and Affiliations

  1. Department of Computer Science, University of Haifa, Haifa, Israel

    Yosi Ben Asher & Vladislav Tartakovsky

  2. IBM HRL, Haifa, Israel

    Irina Lipov

  3. Intel Labs (IDC), Matam, Haifa, Israel

    Dror Tiv

Authors
  1. Yosi Ben Asher
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  2. Irina Lipov
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  3. Vladislav Tartakovsky
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  4. Dror Tiv
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Corresponding author

Correspondence to Yosi Ben Asher.

Additional information

This work is supported by the Israel Ministry of Science, Grant No. 3-10894.

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Ben Asher, Y., Lipov, I., Tartakovsky, V. et al. Generating ASIPs with Reduced Number of Connections to the Register-File. Int J Parallel Prog 45, 1461–1487 (2017). https://doi.org/10.1007/s10766-017-0491-4

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  • DOI: https://doi.org/10.1007/s10766-017-0491-4

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