Skip to main content

Advertisement

SpringerLink
Log in

Software Static Energy Modeling for Modern Processors

  • Published:
International Journal of Parallel Programming Aims and scope Submit manuscript

Abstract

Power and energy estimation tools are essential tools that are used by system designers, software developers and compiler developers to optimize their products. In this work we present a novel method for statically estimating and analyzing the energy and power of programs, the method gives power and energy statistics on the feasible program paths for both the core and cache using symbolic execution.Unlike profile-guided optimizations—that require generating stimulus and running them on the target processor to cover all possible paths—or the dataflow analysis that traverse all control-flow-graph paths, our method traverses all feasible paths of the program. Our method is static, which enables running it at compile time. We demonstrated how the tool can be used to optimize the power and energy of programs at compile time by choosing compiler flags that minimize the energy or power of the program.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

Notes

  1. In this paper we assume that the cycles per LLVM instruction (CPI) is constant for all instructions.

  2. There might be leakage or dynamic power that is consumed by the cache regardless of the executed instruction at the core, this depends on the cache power-management implementation.

  3. More details at Cache Emulator section.

References

  1. McCurdy, C., Marin, G., Vetter, J.S.: Characterizing the impact of prefetching on scientific application performance. In: High Performance Computing Systems. Performance Modeling, Benchmarking and Simulation, pp. 115–135. Springer International Publishing (2014)

  2. Reddi, V.J., et al.: Voltage smoothing: characterizing and mitigating voltage noise in production processors via software-guided thread scheduling. In: Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on. IEEE (2010)

  3. Reddi, V.J., et al.: Voltage emergency prediction: using signatures to reduce operating margins. In: High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on. IEEE (2009)

  4. Popovich, M., Mezhiba, A.V., Friedman, E.G.: Power Distribution Networks with On-Chip Decoupling Capacitors. Springer, New York (2008)

    Book  MATH  Google Scholar 

  5. Lefurgy, C.R., et al.: Active management of timing guardband to save energy in POWER7. In: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture. ACM (2011)

  6. Haj-Yihia, J., et al.: Compiler-directed power management for superscalars. ACM Trans. Archit. Code Optim. 11(4), 48 (2015)

    Article  Google Scholar 

  7. Hönig, T., et al.: SEEP: exploiting symbolic execution for energy-aware programming. In: Proceedings of the 4th Workshop on Power-Aware Computing and Systems. ACM (2011)

  8. Hönig, T., et al.: Proactive energy-aware programming with PEEK. In: 2014 Conference on Timely Results in Operating Systems (TRIOS 14). USENIX (2014)

  9. Een, N., Sörensson, N.: MiniSat: a SAT solver with conflict-clause minimization. Sat 5, 8 (2005)

  10. Tiwari, V., et al.: Instruction level power analysis and optimization of software. In: Journals of VLSI Signal Processing Systems, pp. 223–233 (1996)

  11. Grech, N., et al.: Static analysis of energy consumption for LLVM IR programs. In: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems. ACM (2015)

  12. Lattner, C., Adve, V.: LLVM: A compilation framework for lifelong program analysis & transformation. Code Generation and Optimization, CGO 2004. International Symposium on. IEEE (2004)

  13. Borghesi, A., et al.: Power capping in high performance computing systems. In: Principles and Practice of Constraint Programming. Springer International Publishing (2015)

  14. Gustaffson, J., Ermedahl, A., Lisper, B.: Algorithms for infeasible path calculation. In: OASIcs-OpenAccess Series in Informatics, vol. 4. Schloss Dagstuhl-Leibniz-Zentrum für Informatik (2006)

  15. King, J.C.: Symbolic execution and program testing. Commun. ACM 19(7), 385–394 (1976)

    Article  MathSciNet  MATH  Google Scholar 

  16. Anand, S., Godefroid, P., Tillmann, N.: Demand-driven compositional symbolic execution. In: Tools and Algorithms for the Construction and Analysis of Systems. Springer, Berlin (2008)

  17. Ma, K.-K., et al.: Directed symbolic execution. In: Static Analysis, pp. 95–111. Springer, Berlin (2011)

  18. Staats, M., Pǎsǎreanu, C.: Parallel symbolic execution for structural test generation. In: Proceedings of the 19th International Symposium on Software Testing and Analysis. ACM (2010)

  19. Lam, P., Bodden, E., Lhoták, O., Hendren, L.: The Soot framework for Java program analysis: a retrospective. In: Cetus Users and Compiler Infastructure Workshop (CETUS 2011), vol. 15, p. 35. (2011)

  20. Shao, Y.S., Brooks, D.: Energy characterization and instruction-level energy model of Intel’s Xeon Phi processor. In: Proceedings of the International Symposium on Low Power Electronics and Design. IEEE Press (2013)

  21. David, H., Gorbatov, E., Hanebutte, U.R., et al.: RAPL: memory power estimation and capping. In: 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), pp. 189–194. IEEE (2010)

  22. Cadar, C., Dunbar, D., Engler, D.R.: KLEE: unassisted and automatic generation of high-coverage tests for complex systems programs. OSDI 8, 209–224 (2008)

    Google Scholar 

  23. Coreutils. www.gnu.org/software/coreutils

  24. Haj-Yihia, J., Yasin, A., Asher, Y.B., Mendelson, A.: Fine-grain power breakdown of modern out-of-order cores and its implications on Skylake-based systems. ACM Trans. Archit. Code Optim. 13(4), 56 (2016)

    Article  Google Scholar 

  25. Intel.: Intel-64 and ia-32 architectures software developer’s manual, Volume 3A: System Programming Guide, Part 1.64 (2013)

  26. Chen, Y., Huang, Y., Eeckhout, L., Fursin, G., Peng, L., Temam, O., Chengyong, W.: Evaluating iterative optimization across 1000 datasets. ACM Sigplan Notices 45(6), 448–459 (2010)

    Article  Google Scholar 

  27. Eeckhout, L., Vandierendonck, H., De Bosschere, K: Workload design: selecting representative program-input pairs. In: Parallel Architectures and Compilation Techniques, 2002. Proceedings. 2002 International Conference on, pp. 83–94. IEEE (2002)

  28. Cammarota, R., Nicolau, A., Veidenbaum, A.V., Kejariwal, A., Donato, D., Madhugiri, M.: On the determination of inlining vectors for program optimization. In: International Conference on Compiler Construction, pp. 164–183. Springer, Berlin (2013)

  29. Ferdinand, C., Wilhelm, R.: Efficient and precise cache behavior prediction for real-time systems. Real Time Syst. 17(2–3), 131–181 (1999)

    Article  Google Scholar 

  30. Chattopadhyay, S., Roychoudhury, A.: Scalable and precise refinement of cache timing analysis via path-sensitive verification. Real Time Syst. 49(4), 517–562 (2013)

    Article  MATH  Google Scholar 

  31. Wagemann, P., et al.: Worst-case energy consumption analysis for energy-constrained embedded systems. In: Proceedings of the 27th Euromicro Conference on Real-Time Systems (ECRTS). IEEE (2015)

  32. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations, vol. 28, pp. 83–94. ACM (2000)

  33. Ye, W., Vijaykrishnam, N., Kandemir, M., Irwin, M.: The design and use of simplepower: a cycle accurate energy estimation tool. In: Proceedings of the Design Automation Conference DAC’00 (June 2000)

  34. Fursin, G., Miceli, R., Lokhmotov, A., Gerndt, M., Baboulin, M., Malony, A.D., Chamski, Z., Novillo, D., Del Vento, D.: Collective mind: towards practical and collaborative auto-tuning. Sci. Program. 22(4), 309–329 (2014)

    Google Scholar 

  35. Kadayif, I., Kandemir, M., Chen, G., Vijaykrishnan, N., Irwin, M.J., Sivasubramaniam, A.: Compiler-directed high-level energy estimation and optimization. ACM Trans. Embed. Comput. Syst. 4(4), 819–850 (2005)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, Haifa University, Haifa, Israel

    Jawad Haj-Yihia & Yosi Ben-Asher

Authors
  1. Jawad Haj-Yihia
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yosi Ben-Asher
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jawad Haj-Yihia.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Haj-Yihia, J., Ben-Asher, Y. Software Static Energy Modeling for Modern Processors. Int J Parallel Prog 46, 284–312 (2018). https://doi.org/10.1007/s10766-017-0496-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10766-017-0496-z

Keywords

Search

Navigation